公开(公告)号：JPH06204842A

公开(公告)日：1994-07-22

申请号：JP17398993

申请日：1993-07-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H03K19/0175 ,  H03K19/0185 ,  H03M5/14 ,  H03K5/13

Abstract: PURPOSE: To provide a logic interface circuit which restores phase and data information from differential input signals, having distorted duty cycles generated by ECL(emitter coupled logic)-CMOS translators. CONSTITUTION: A logical interface circuit incorporates first and second ECL- CMOS translators T1 and T2, first and second delay circuits, and an output logic circuit. The first delay circuit incorporates a first inverter I1, a first delay network D1, and a first NAND logical gate N1 and the second delay circuit incorporates a second inverter 12, a second delay network D2, and a second NAND logical gate N2. The output logic circuit incorporates a third NAND logical gate. The interface circuit generates an output signal, the cycle time of which can be detected for defining frequency information and which has the shape of a pulse train, in which the presence/absence of pulses can be detected for defining data information.

公开(公告)号：JPH02262374A

公开(公告)日：1990-10-25

申请号：JP3506090

申请日：1990-02-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/0812 ,  H03K17/16 ,  H01L29/784

Abstract: PURPOSE: To obtain a simple system at a reasonable manufacturing cost for protecting an electronic component by a method wherein a transmission gate possessed of a source and a drain as an input and an output respectively is connected to the input of a MOS component gate. CONSTITUTION: An electrostatic protective system is used together with a voltage-responsive MOS component 50 possessed of a gate input and provided with an oxide layer previously prescribed in thickness, wherein the protective system comprises the MOS component 50 provided with a gate input 52 and a transmission gate 54 possessed of a source and a drain as an input and an output respectively, and the transmission gate 54 is connected to the gate input 52 of the MOS component 50 so as to protect the MOS component 50 against discharge caused by a sudden electric voltage surge. For instance, the above transmission gate 54 comprises a thick oxide layer which is substantially thicker than the oxide layer of the gate input 52 of the MOS component 50. The above protective system comprises also a well-known ESD circuit 56.

公开(公告)号：JPH02246417A

公开(公告)日：1990-10-02

申请号：JP3505990

申请日：1990-02-15

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H03K5/151

Abstract: PURPOSE: To secure a more uniform pulse width in a clock phase at a high working frequency by providing two inverters and a NOR gate. CONSTITUTION: A NOR gate 46 and inverters 42 and 44 respectively have delaying functions and, when a clock signal becomes 'high', an inverted clock(CKB) 4 signal first becomes 'low' before an output clock(CK) becomes 'high', because the gate 46 is switched earlier than the inverters 42 and 44. When the clock signal becomes 'low', the CKB signal does not become 'high' until the CK signal becomes 'low', because the input to the gate 46 through a line 52 is not generated until both inverters 42 and 44 become active. Therefore, a circuit 40 operates with a shorter delay and a more uniform pulse width phase.