公开(公告)号：JPH07273796A

公开(公告)日：1995-10-20

申请号：JP1213395

申请日：1995-01-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AREN SOO

IPC: H04L12/56 ,  H04Q11/04

Abstract: PURPOSE: To provide a modular switching architecture for a high-speed packet network. CONSTITUTION: A line interface device LID 40 of the architecture gives frame data in the HDLC form and a clock to a frame relay packet management device FRYPAM 44. The reception FRYPAM 44 performs CRC check, table look-up, and DLCI field conversion to write reception frames having correct FCS fields in a frame buffer and communicates with another FRYPAM 54 to update a transmission queue. A transmission FRYPAM 54 reads out frames from a buffer 46 to send them to a transmission LID coupled to a destination. The transmission LID 50 converts HDLC data to a proper form to transmit frames to the destination terminal. A frame buffer manager 62 assigns the buffer 46 to the FRYPAM 44.

公开(公告)号：JPH07321842A

公开(公告)日：1995-12-08

申请号：JP10749595

申请日：1995-05-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AREN SOO

IPC: H04L29/06 ,  H04L12/56

Abstract: PURPOSE: To obtain a switchable line interface module by allowing a packet switching network to interface with plural transmitting/receiving data terminals. CONSTITUTION: Asynchronous ports 0 to N in a line interface device(LID) support the transmission (Tx) and reception (Rx) of data and control bits CNTL. A line transceiver 604 converts a receiving signal level into a system logic level and sends the logical level signal to an N-port universal asynchronous receiver/transmitter(UART) 606. A microprocessor 610 exchanges data between a RAM 608 and the UART 606. An HDLC controller 616 adds DLCI based on information outputted from an LID controller 614 to form an HDLC frame to be sent to an FRYPAM. On the receiving side, information on an input line is physically converted into data consisting of a signal CLK and the HDLC to interface with a specific data terminal in the system.