公开(公告)号：JPH0850568A

公开(公告)日：1996-02-20

申请号：JP12128195

申请日：1995-05-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIERAADO TEI MATSUKII ,  BIKUTAA EFU ANDOREIDO ,  KERII MAKUKOODO HOOTON

IPC: G06F13/36 ,  G06F13/40

Abstract: PURPOSE: To provide an integrated processor which uses an improved address decode method between bus cycles of an external master. CONSTITUTION: An external PCI master can start a cycle (either memory or input-output) on a PCI bus 518 by asserting an address signal to the PCI bus 518. A bus interface unit 510 transfers the address signal to a CPU local bus 508. A decode logic in memory or input-output controllers 504 and 506 decodes the address signal and decides whether the address is mapped in an address space of each of the controllers 504 and 506. If the address exists in a mapped space of each of the controllers 504 and 506, the controllers 504 and 506 assert a hit signal and notifies the unit 510 that the address is mapped to a device positioned on the bus 508.

公开(公告)号：JPH08202563A

公开(公告)日：1996-08-09

申请号：JP18678895

申请日：1995-07-24

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU DEII GEFUAATO ,  JIEIMUZU AARU MAKUDONARUDO ,  BIKUTAA EFU ANDOREIDO

IPC: G06F11/22 ,  G06F9/48 ,  G06F11/14 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To provide a computer system provided with an interruption driving system management mode for accessing a system management code. SOLUTION: A lock-out register is provided so as to evade access to the system management code while this computer system is operated in a normal mode. An interruption control unit 204 is connected to the ICE interruption line of a microprocessor core and a memory control unit 208 is controlled corresponding to the assertion of external 'debugging' interruption signals and external SMM interruption signals. During a normal operation, the microprocessor core executes a code from the 'normal' memory area of a system memory.

公开(公告)号：JPH0883236A

公开(公告)日：1996-03-26

申请号：JP12118895

申请日：1995-05-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIERAADO TEI MATSUKII ,  BIKUTAA EFU ANDOREIDO ,  KERII MAKUKOODO HOOTON

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/78

Abstract: PURPOSE: To reduce the space of a circuit and an on-chip for address decoders by integrating the address decoders to one location. CONSTITUTION: When a processor starts a given local bus cycle, the processor asserts an address to an address bus to inform of the start of the local bus cycle. Decode logics within a memory controller 504 and an input/output controller 506 decide whether addresses are respectively directed to an memory or an input/output address space. If they are directed, each controller asserts a it signal and informs a bus interface 510 that a present cycle is directed to a device in a CPU local bus 508 and that the bus interface device should not start an external PCT bus cycle.