公开(公告)号：JPH0850574A

公开(公告)日：1996-02-20

申请号：JP4973695

申请日：1995-03-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAIAN DEII MAKUMIN ,  SUTEIIBUN SHII HOON

IPC: G01R31/28 ,  G01R31/30 ,  G06F1/04 ,  G06F1/06 ,  G06F11/22 ,  G06F15/78 ,  H03K3/02 ,  H03K5/13

Abstract: PURPOSE: To provide a test structure which contains a variable control delay element and its method. CONSTITUTION: During a normal operation, multiplexers 202A to D inserted in a delay chain 104 are constructed so that plural variable delay units 106A to D are electrically and serially connected with one another. An external command signal to start a test operation where the units 106A to D are tested for predictable defect is given to a microprocessor. During the test operation, a control unit selects the multiplexers 202A to D so that four units 106A to D may be electrically disconnected from one another. Common test signals are simultaneously driven through more than two units 106A to D, and whether the transition of common pulse signals are transmitted substantially at the same time through each unit 106A to D by means of a comparator which is associated with output of each unit 106A to D.

公开(公告)号：JPH088699A

公开(公告)日：1996-01-12

申请号：JP4973895

申请日：1995-03-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAIAN DEII MAKUMIN ,  SUTEIIBUN SHII HOON

IPC: G01R31/28 ,  G01R31/30 ,  H03H11/26 ,  H03K5/13

Abstract: PURPOSE: To provide a test constitution and method for easily testing whether or not any micro defect is present in a variable control delay element in a clock generator circuit. CONSTITUTION: A delay chain 104 is used in a clock generator circuit which generates the inside clock signal of a microprocessor. During a normal operation, a pair of multiplexers 202 interpolated in the delay chain 104 are constituted so that plural variable delay units 106 can be electrically and serially connected. During a test operation, when the multiplexers 202 are set in a test mode, the four delay units 106 are electrically separated. A common test signal is simultaneously driven through more than two variable delay units 106, and whether or not the transition of the common pulse signal is propagated through each variable delay unit 106 at the same time, is judged by a comparator circuit connected with the output of each variable delay unit 106.

公开(公告)号：JPH04225456A

公开(公告)日：1992-08-14

申请号：JP5989291

申请日：1991-03-25

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURAIAN DEII MAKUMIN ,  SUMIITA GUPUTA

IPC: G06F9/30 ,  G06F9/34 ,  G06F13/36 ,  G06F13/40

Abstract: PURPOSE: To manage data which efficiently uses a space in a layout while efficiency is maintained in operation by inputting a data word to a data operation device in a precise hierarchy arrangement at time intervals which a data operation device, a register device, a data bus and a clock source have cooperatively and continuously selected. CONSTITUTION: At least one data operation device 14 for executing the operation on a data phrase, at least one register 36 for storing data and the data bus for transmitting various data are contained. The data bus is operationally connected to the data operation device 14, the register 36 and the storage device. Furthermore, at least one clock source for establishing plural time intervals is contained.