公开(公告)号：JPH07312395A

公开(公告)日：1995-11-28

申请号：JP9839495

申请日：1995-04-24

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO KEI WAI RIU ,  YUU SAN ,  CHII CHIYAN

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To reduce the whole size of a cell without damaging perfectibility of tunnel oxide, by arranging a stacked gate edge on a semiconductor device, forming a spacer on the stacked gate edge, protecting it, and executing self- alignment source etch. CONSTITUTION: A flash EPROM cell 100 contains an oxide region 104 between a first polysilicon layer 102 and a second polysilicon layer 103, and contains a tunnel oxide region 106 between a polysilicon layer 102 and a silicon region 108. A stacked gate edge 502 is formed in the polysilicon region 102. By using spacer 504 formation, the stacked gate edge 502 is protected from being exposed to a self-alignment source process. Thereby safety of tunnel oxide is improved, a uniform source region for spacer formation is generated, and source injection is not given to a part in which silicon is eliminated.