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公开(公告)号：JPH07152584A
公开(公告)日：1995-06-16
申请号：JP22433594
申请日：1994-09-20
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To provide a computer system provided with a peripheral device capable of asserting interruption request signals and an interruption controller provided with at least one interruption request line suited for reducing power consumption for receiving the interruption request signals. CONSTITUTION: This interruption controller 20 is provided with a control circuit 118 capable of generating microprocessor interruption signals INT in response to the assertion of the interruption request signals IR0 -IR1 and an under- processing register 124 for storing data for displaying whether or not a specified interruption request is under a processing at present by a microprocessor. A power management unit 10 is connected to the output line of the under- processing register 124 and controls clock signals or power supplied to this computer system by the data stored inside the under-processing register 124.
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公开(公告)号：JPH07182277A
公开(公告)日：1995-07-21
申请号：JP26396894
申请日：1994-10-27
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To provide a DMA byte lane selection method for peripheral devices and a computer system where this method is built in. CONSTITUTION: A direct memory access controller 102 executes a memory access cycle and an I/O access cycle to realize the 2-cycle method for execution of desired DMA transfer. In the memory access cycle, the address position of a system memory 106 to be accessed is driven onto an address designation line of a local bus 110. In the I/O access cycle, the address value in a DMA constitution address range is driven onto an address line of the local bus 110. In the I/O access cycle, lower two bits of the address value are encoded to give byte lane information to a peripheral device 108. The peripheral device 108 receives or gives data of a specific byte lane in response to them.
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公开(公告)号：JPH07210537A
公开(公告)日：1995-08-11
申请号：JP30445494
申请日：1994-12-08
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAGURASU DEII GEFUAATO , DAN ESU MAJIETSUTO
Abstract: PURPOSE: To provide a computer system with which the cost of an entire integrated processor is minimized, while keeping wide compatibility and high performance. CONSTITUTION: A computer system 200 is provided with a peripheral bus 220 equipped with a multiplex address/data line, latch 225 having the input port connected to an address/data line 220, and integrated processor 210. The processor 210 is provided with a CPU core 240, bus interface unit 242 for interfacing the data, addresses and control signals between a local bus 248 and the peripheral bus 220, and local bus control unit 244 capable of generating a load signal showing the existence of an effective address for the peripheral bus 220, while being connected to the local bus 248. Further, this computer system is provided with a peripheral device 230 having the address line connected to the output port of the latch 225 and the data line connected to the address/data line of the peripheral bus 220.
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公开(公告)号：JPH08171500A
公开(公告)日：1996-07-02
申请号：JP18426195
申请日：1995-07-20
Applicant: ADVANCED MICRO DEVICES INC
Inventor： MAIKERU DEI PEDONIYUU , HANSU MAGUNUTSUSON , DAN ESU MAJIETSUTO
Abstract: PROBLEM TO BE SOLVED: To provide a computer system adding a microprocessor core capable of efficiently processing a system managing function and also supporting the in-circuit emulation mode of a system managing code. SOLUTION: The computer system is the one adding the microprocessor core 202 including an interruption input line, an interruption control unit 204 which is connected to the interruption input line and receives a debug interruption signal and an SMM interruption signal, a system memory 210 and a memory control unit 208 which is connected to the processor core and a memory modeline. The computer system enables entering the in-circuit emulation mode while the microprocessor core is executed outside of the system managing space of the system memory by asserting the debug interruption signal.
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Patent Agency Ranking5.发明专利
公开(公告)号：JPH07302240A
公开(公告)日：1995-11-14
申请号：JP1242095
申请日：1995-01-30
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To allow a computer system to support a peripheral equipment without increasing the number of pins of an integrated processor by controlling a data buffer and an address latch with a sub bus control unit to guide a low- performance bus from a multiple peripheral bus to the outside. CONSTITUTION: A peripheral interconnection bus 220 consisting a PCI standard bus acts like adjusting data transfer between an internal bus of an integrated processor 210 and a PCI peripheral equipment 222. The integrated processor 210 has a sub bus control unit to generate a side band control signal and external introduction of a low performance 2nd bus as an ISA bus is realized by using the side band control signal without the need for one complete set of external pins for the integrated processor 210 for a 2nd bus. The introduction of the 2nd bus is conducted by using an external data buffer 224 and an external address latch 226 controlled by the side band control signal. Thus, the high- performance peripheral equipment is supported without much increasing the number of pins of the integrated processors 210.
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公开(公告)号：JPH0934781A
公开(公告)日：1997-02-07
申请号：JP17222295
申请日：1995-07-07
Applicant: ADVANCED MICRO DEVICES INC
IPC: G06F12/06
Abstract: PROBLEM TO BE SOLVED: To provide an integrated system with which different address lines and data lines for a RAM and ROM can be combined with a memory system made into a unit. SOLUTION: The memory system is provided with a memory controller 100 for reducing the pin count of the integrated system by combining the functions of a RAM controller and a ROM controller with one unit and sharing the address line and data line. This memory controller is provided with a cycle and address decoder 225 for judging whether the address is turned toward a RAM array or toward a ROM array by receiving the address from a local bus 165 and comparing that address with the information stored in constitution registers 285 and 295.
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公开(公告)号：JPH07182276A
公开(公告)日：1995-07-21
申请号：JP26396794
申请日：1994-10-27
Applicant: ADVANCED MICRO DEVICES INC
Abstract: PURPOSE: To provide a direct memory access controller which executes a memory access cycle and an I/O access cycle to perform DMA transfer. CONSTITUTION: In the memory access cycle, the address position of a system memory 106 to be accessed is driven onto an address designation line of a local bus 110. In the I/O access cycle, an address value within a DMA constitution address range is driven into an address line on the local bus 110. The DMA constitution address range is the range of the address value where a constitution register of a DMA controller 102 is mapped for the purpose of receiving initialization data. Another peripheral device 108 which can be connected to the local bus 110 doesn't respond to the I/O access cycle. An address disable signal to disable the address decoder of another I/O peripheral device which is not related to DMA transfer is unnecessary. A subsystem to respond to a special DMA protocol is unnecessary.
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8.发明专利
公开(公告)号：JPH07182204A
公开(公告)日：1995-07-21
申请号：JP26967094
申请日：1994-11-02
Applicant: ADVANCED MICRO DEVICES INC
Inventor： HANSU ERU MAGUNATSUSON , DAGURASU DEII GEFUAATO , DAN ESU MAJIETSUTO
IPC: G06F11/28 , G01R31/3185 , G06F11/36 , G06F15/78
Abstract: PURPOSE: To provide a debugging tool which tests components of an integrated microprocessor in various operation states. CONSTITUTION: In this integrated processor 10, one or more function units and stand-alone microprocessors are laid out on a common semiconductor die 25 and are connected by a common local bus 30. When receiving a test command signal generated on the outside of the integrated processor 10 from a host computer, a test circuit which is arranged on the die 25 and is connected to the common bus 30 generates a local bus cycle for stand-alone microprocessors or function units and/or devices attached to them in response to this command signal. In one example, the integrated processor 10 is built in the mother board of a target computer connected to the host computer by a JTAG bus or another test protocol bus.
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公开(公告)号：JPH0756641A
公开(公告)日：1995-03-03
申请号：JP13865294
申请日：1994-06-21
Applicant: ADVANCED MICRO DEVICES INC
Inventor： DAN ESU MAJIETSUTO
Abstract: PURPOSE: To provide a thermal sensor mechanism which controls the operation of a logic circuit so that the logic circuit can be maintained at a proper temperature. CONSTITUTION: This mechanism includes a thermal sensor 6 integrated in the junction of a logic circuit, which detects the temperature of the junction. This mechanism also includes a temperature feedback signal 8 indicating the temperature sensed by the thermal sensor at the function. The temperature feedback signal is an input to a clock frequency-dividing circuit 4 of this mechanism. The clock frequency-dividing circuit receives an input clock signal, and outputs the output clock signal of a frequency decided by the clock frequency-dividing circuit based on the temperature feedback signal received by the clock frequency-dividing circuit. The output clock signal functions as an input for driving the logic circuit.
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