公开(公告)号：JPH03190416A

公开(公告)日：1991-08-20

申请号：JP34117990

申请日：1990-11-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DONARUDO EMU UORUTAASU JIYUNIA

IPC: H03K5/151 ,  H03K5/15 ,  H03K19/00

Abstract: PURPOSE: To adjust superposed voltage by connecting respective means so that a 2nd phase clock signal is received by a 1st phase clock generation circuit means connected to a 1st delay means and a 1st phase clock signal is received by a 2nd phase clock generation circuit means. CONSTITUTION: A clock generator 8 for generating a level phase clock signal ϕ1 from a node X on an output line 10 and generating a level phase clock signal ϕ2 from a node Y on the output line 14 is formed by a 1st delay circuit 16, a 1st phase clock generation circuit 18, a 2nd delay circuit 20, and a 2nd phase clock generation circuit 22. The circuit 22 has a 1st input connected to the output of an inverter INV1 and a 2nd input connected to the output line 10 through a line 26 and the node X. An output from the circuit 22 is regulated by the node Y. Consequently adjustable superposed voltage can be obtained.