公开(公告)号：JPH0628309A

公开(公告)日：1994-02-04

申请号：JP10437993

申请日：1993-04-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU JIEI RUNARUDEYUU ,  FUIRITSUPU NGAI

IPC: G06F13/36 ,  G06F12/02 ,  G06F13/40

Abstract: PURPOSE: To reduce the cost of the buffer memory of a peripheral device by using prefetch and giving prefetched data to a bus at the time when the next memory address matches with a forecasted memory address. CONSTITUTION: A local data bus is converted from 16-bit width to 8-bit width, and a single 8-bit width DRAM chip 10 and a PROM chip 11 are used. A local memory read sequence is executed in response to a memory read command from an ISA bus including a memory fetch address, and the memory fetch address matches the forecasted next address. The forecasted next address is incrementation of the next but one memory fetch address derived from the ISA bus. In response to suggestion of matching, data derived from the forecasted next address position is immediately presented to an ISA system data bus. This operation is completed in a minimum access time of ISA bus specifications.

公开(公告)号：JPH0634718A

公开(公告)日：1994-02-10

申请号：JP10414293

申请日：1993-04-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TOOMASU JIEI RUNARUDEYUU ,  FUIRITSUPU NGAI

IPC: G01R31/28 ,  G01R31/3185

Abstract: PURPOSE: To enhance capability for attaining diagnostic information of a chip, without increasing the pin-out by providing AND and OR gates to be connected with an arbitrary number of chip nodes and can be combined under control of a software program, to produce a combined output of dedicated output pin. CONSTITUTION: A metal interconnection line 38 for connecting M nodes 37 available for diagnosis with a programmable AND gate is provided on a chip and connected through M interconnection lines 39 with a programmable OR gate 4O'. A first bit, i.e., a register ANDOR bit 32 to be connected with an MUX 46, switches the output of the MUX 46 between lines 44, 45. Similarly, a second polarity bit 33 causes polarity switching of output by inverting an XOR circuit 48. A third stretch bit 34 is connected with a pair of AND gates 50. When the stretch bit is low, the gate 50 bypasses a pulse stretcher 51 on a line 52 to a signal from the XOR 48. If bit 34 is high, output from the XOR 48 is passed through the circuit 51 and connected with a pin-out (j).