公开(公告)号：JPH0758557A

公开(公告)日：1995-03-03

申请号：JP14139794

申请日：1994-06-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEFURII II BUREEMAA

IPC: H03F3/45

Abstract: PURPOSE: To make an operational amplifier operable at a low power supply voltage by making the output of the amplifier swingable substantially over the full voltage range of a power source and, at the same time, to enable the amplifier adaptable to an output range performance request which is seen in the application of a high voltage. CONSTITUTION: An amplifier 4 is designed so that the amplifier 4 may have the minimum voltage drop through p-channel source transistors 120, 124, and 128 and the output 114 of the amplifier 4 may swing over a wide range. Namely, a DC bias circuit works to establish a bias voltage at a transistor 124 in a current source, at transistors 132 and 136 in a current sink, and at transistors 122, 126, 130, 134, and 138 in a cascode device. Therefore, current mirror operations between transistors 128 and 120 and current sink between the transistors 132 and 136 cause each transistor to stay in a saturated area against all swinging values of the output 114.

公开(公告)号：JPH0253311A

公开(公告)日：1990-02-22

申请号：JP16824889

申请日：1989-06-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEFURII II BUREEMAA ,  HARII ESU JIYAKUSON

IPC: G06G7/25 ,  H03G11/00

Abstract: PURPOSE: To clamp differential output voltage to a fixed level independently of process and the fluctuation of temperature by connecting the conduction path electrode of the 2nd N (P)-channel clamping transistor between the 2nd input-output nodes and also accepting an N (P)-bias signal. CONSTITUTION: A conduction path that is regulated by source and drain electrodes of clamping transistors P0 and N10 is connected between the 1st input node A and the 1st output node C in parallel with the 1st feedback resistor R3. A conduction path that is regulated by the source and drain electrodes of clamping transistors P12 and N12 is connected between the 2nd input node B and the 2nd output node D in parallel with the 2nd feedback resistor R4. Further, gates of the transistors N10 and N12 are connected to receive an N-channel bias signal N-BIAS. Thereby, output voltage is clamped to a constant voltage level.

公开(公告)号：JPH06204820A

公开(公告)日：1994-07-22

申请号：JP26055193

申请日：1993-10-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEFURII II BUREEMAA

IPC: G01R19/165 ,  H03K3/3565 ,  H03K5/08

Abstract: PURPOSE: To provide an improved comparator circuit for generating a resulting digital output by comparing two input signals with each other. CONSTITUTION: This comparator circuit 10 uses a single cascode device and a current mirror circuit 22, which are connected in parallel with two differential amplifier stages 12 and 14. One of the stages 12 and 14 receives differential input signals, and the other receives a variable reference voltage and a feedback voltage from the output of the comparator 10. The reference voltage is changed according to a request from a user. The reference voltage can be changed to any voltage within the range of input signals given to the differential amplifier stage. The hysteresis differential voltage of the input differential amplifier stage can be controlled accurately, by changing a bias current given to the hysteresis differential amplifier stage and the reference voltage.