公开(公告)号：JPH0675779A

公开(公告)日：1994-03-18

申请号：JP15236693

申请日：1993-06-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIMUZU II BOURUZU ,  MAAKU RUETOUKE ,  DEIRU II GURITSUKU

IPC: G06F1/24 ,  G06F9/48 ,  G06F13/24 ,  G06F9/46

Abstract: PURPOSE: To enable and disable interruption by a software by providing a structure for indicating software and hardware situations, and a structure for generating interruption when the assertion of an interruption request signal is generated. CONSTITUTION: When a processor is turned into an idle mode, an IDLE INDICA TOR CIRCUIT 22 asserts an IDLE signal on a line 24, the output of an OR gate 28 is turned to a high level, and as long as the level is held, a latch 10 is set by the assertion of an interruption request signal INTO on a line 4, and interruption is generated. Then, while the processor is in the IDLE mode, an interruption flag IEO is set by the assertion of the interruption request signal INTO, and even when the interruption is masked by software, it is recognized by the processor. Also, when the processor is not in the idle mode, the IDLE signal on the line 24 is remaining in a low level, and the possibility and impossibility of the interruption is decided by a SOFTWARE ENABLE signal on a line 26.

公开(公告)号：JPH0222742A

公开(公告)日：1990-01-25

申请号：JP7792289

申请日：1989-03-28

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BURUUSU RANDARU AREN ,  AASAA BENJIYAMIN ORIBAA ,  ROBAATO DABURIYU OODERU ,  JIEIMUZU II BOURUZU

IPC: G06F11/30 ,  G06F11/00

Abstract: PURPOSE: To improve the reliability of a watchdog timer by resetting a program control processor when elapsed time indicated by a timer code exceeds a time period indicated by a preset code. CONSTITUTION: A CPU 100 and a system clock 101 transmit control information through a line 104. This watchdog timer 105 receives system clocks through the line 102 and communicates the control information with the CPU 100 through the line 106. The timer 105 stores a code for indicating the time period within which the CPU 100 is required to generate display signals. The display signals are supplied from the CPU 100 through a bus 107 under program control. When the display signals are not generated within the period, watchdog timer reset signals DTRST are supplied to a reset driver 108 on the line 110. In such a manner, the reliability of the timer is improved.

公开(公告)号：JPH06195476A

公开(公告)日：1994-07-15

申请号：JP16999993

申请日：1993-07-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIMUZU II BOURUZU ,  ROBAATO OOBURIN

IPC: G06F15/78 ,  G06F1/32 ,  G06F13/40 ,  H03K19/017 ,  H04Q7/32 ,  H04Q7/38 ,  H04B7/26

Abstract: PURPOSE: To provide a weak pull-up disabling method used in relation to a microcontroller which is incorporated in an integrated circuit and its mechanism. CONSTITUTION: Weak pull-up disabling mechanism is incorporated in the integrated circuit adding the microcontroller 40. The mechanism disables the weak pull-upt of an I/O buffer in the microcontroller 40. Weak pull-up is functioned so as to pull-up the voltage of a related port to high. Weak pull-up is disabled so that the necessity of a driver for sinking current in an input mode is removed. The removal of the necessity of the external driver by weak pull-up disabling mechanism reduces the power consumption of the integrated circuit.

公开(公告)号：JPH06301439A

公开(公告)日：1994-10-28

申请号：JP500994

申请日：1994-01-21

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIMUZU II BOURUZU

IPC: G06F1/06 ,  G06F1/08

Abstract: PURPOSE: To provide a device which controls a clock driver signal for computer in response to a selected input signal. CONSTITUTION: Thus device for controlling clock driver signal is provided with a first frequency converter 32 which receives a system clock signal having a system clock frequency and generates a first repetitive pulse having a first repetitive clock frequency in response to the system clock signal. A second frequency converter 34 is actively connected to the first frequency converter 32, receives the first repetitive clock signal, and generates a second repetitive or internal clock signal having a second repetitive frequency in response to the first repetitive signal. A switching device 36 is actively connected to the frequency converters 32 and 34 and generates the first repetitive clock signal as its output (clock driver signal) when a selected input signal is in a first state. When the selected input signal is in a second state, the device 36 generates the second repetitive clock signal as its output.

公开(公告)号：JPH06103146A

公开(公告)日：1994-04-15

申请号：JP15229493

申请日：1993-06-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIRU II GURITSUKU ,  JIEIMUZU II BOURUZU

IPC: G06F1/04 ,  G06F1/32 ,  G06F12/00 ,  G11C8/18

Abstract: PURPOSE: To provide a processing system which has a processor which accesses an external memory for data and/or instructions. CONSTITUTION: An improved external memory access control system makes the duration of external memory enabling independent of the number of external memory accesses per unit time to reduce the consumption power of a processing system. The control system includes a selectively programmable clock, which gives a clock signal having one of at least two speeds to determine the external memory access speed, and a enabling duration control structure coupled to this clock. They are so arranged that the external memory is enabled in the duration of each memory access independent of the external memory access speed. This structure includes a sub-structure which changes the duty cycle of an external memory enabling duration control signal based on the selected clock speed.