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公开(公告)号:JPH088845A
公开(公告)日:1996-01-12
申请号:JP1261695
申请日:1995-01-30
Applicant: ADVANCED MICRO DEVICES INC
Inventor: JIYAKURIIN MARINZU , JIYOSEFU DABURIYU PIITAASON , JIYON BAATOKOUIATSUKU , ARAN EFU HENDORITSUKUSON
Abstract: PURPOSE: To provide a controller in which design of a new controller by every change of a data processing method is unnecessitated and which is designed not to depend on internal data processing ability very much. CONSTITUTION: An intermediate data processing of a digital signal outside an integrated circuit is selectively made possible by a system 10 and a transcoder 101, a codec 102 connected to the transcoder 101 and a data processor located outside time IC are included in the system 10. The digital signal is switched between the transcoder 101 and the codec 102 by responding to a strobe signal and transmitted to a data route of an external processor by a programmable switch. The digital signal is formatted in the IC and processed by the external processor. The digital signal which is processed outside is returned from the external processor to the IC with the data route. After that, the digital signal is formatted again in the IC and further processed by the IC.
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公开(公告)号:JPH07327326A
公开(公告)日:1995-12-12
申请号:JP1613695
申请日:1995-02-02
Applicant: ADVANCED MICRO DEVICES INC
Inventor: ARAN EFU HENDORITSUKUSON , JIYOSEFU DABURIYU PIITAASON
Abstract: PURPOSE: To achieve a battery protection and a sleep synchronous control efficiently at a low cost in a battery-driven device. CONSTITUTION: A power management circuit 10 for a battery-driven device is designed, such that sleeps is induced during a predetermined period when the device is not used, has an oscillator 12 for generating a clock signal, and has a battery monitor sub-circuit 14 for indicating when a predetermined low battery power state is reached, which includes a sub-circuit that allows the oscillator to generate a clock signal and a sub-circuit that responds to an instruction that the predetermined low battery state has been reached from a battery monitor sub-circuit. The sub-circuit interrupts the operation of the sub-circuit, that allows the oscillator to generate a clock signal.
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公开(公告)号:JPH07326977A
公开(公告)日:1995-12-12
申请号:JP1571695
申请日:1995-02-02
Applicant: ADVANCED MICRO DEVICES INC
Inventor: ARAN EFU HENDORITSUKUSON , JIYOSEFU DABURIYU PIITAASON
Abstract: PURPOSE: To form a receiver quality measuring system improved for a digital cordless telephone and similar devices. CONSTITUTION: The communication circuit 10 is connected to a radio receiver 12 so as to receive a data signal and a received signal intensity indicator expressing the intensity of a radio carrier from the receiver 12 and connected also to a controller. The communication circuit includes four sub-circuits. The 1st sub-circuit 20 receives the received signal intensity indicator from the receiver 12, judges its radio carrier intensity and transfers intensity information to the controller. The 2nd sub-circuit 28 receives a data signal from the receiver 12, judges the existence of a bit error and transfers the judged result to the controller. The 3rd sub-circuit 24 receives the data signal from the receiver 12, judges the existence of jitter and transfers the judged result to the controller. The 4th sub-circuit 30 receives outputs from the 2nd and 3rd sub-circuits 28, 24 and the controller and suppresses signal noises.
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公开(公告)号:JPH07321869A
公开(公告)日:1995-12-08
申请号:JP1571795
申请日:1995-02-02
Applicant: ADVANCED MICRO DEVICES INC
Inventor: ARAN EFU HENDORITSUKUSON , JIYOSEFU DABURIYU PIITAASON
Abstract: PURPOSE: To obtain a radio frequency(RF) interface circuit capable of supporting either one of in-phase orthogonal phase (I-Q) and non-return-to-zero (NRZ) RF transmitter architectures by one integrated circuit(IC). CONSTITUTION: In the dual mode base band control device, either one of I-Q and NRZ RF transmitter architectures can be supported by one IC to use the device for a 2nd generation cordless telephone. An RF interface circuit 11 controls an output signal to support the I-Q or NRZ architecture depending on a MODE control bit received from a control IC. The circuit 11 includes an I-Q waveform generator 12, four multiplexers 13 to 16, two digital/analog converters 17, 18, a buffer 19, an interconnection circuit, and a timing controller 25 to be driven by constitutable software control 24.
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