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    PROGRAMABLE LOGIC ARRAY DEVICE
    3.
    发明专利
    PROGRAMABLE LOGIC ARRAY DEVICE 失效

    公开(公告)号：JPH08256052A

    公开(公告)日：1996-10-01

    申请号：JP4278996

    申请日：1996-02-29

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： OOMU AGURAWARU ,  KAPIRU SHIYANKAA ,  FUARASU ENU MUBARAKU

    IPC: G01R31/3185 ,  G06F7/00 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To improve the flexibility of design by providing a programmable combination logic circuit, a data node, an output storage element and a programmable outputting means which supplies a selection signal of a data output of a storage element as an output to the data node and making a logic circuit output programmable. SOLUTION: A common synchronous preset signal and a common asynchronous reset signal are given to four output register parts 16 of a PLA device 10, four output macro cells 18 and a register in six buried register parts 20 in common. The common synchronous preset signal is given as a term of a product from an output of a programmable AND array 22 to a line 29b. The common synchronous preset signal or the asynchronous reset signal are realized in another logic circuit such as a term of product-sum. The function of the device 10 is improved by a control signal that is given to six field programmable fuses 32, etc.

    PROGRAMABLE LOGIC ARRAY DEVICE
    4.
    发明专利
    PROGRAMABLE LOGIC ARRAY DEVICE 失效

    公开(公告)号：JPH08256053A

    公开(公告)日：1996-10-01

    申请号：JP4279096

    申请日：1996-02-29

    Applicant: ADVANCED MICRO DEVICES INC

    Inventor： OOMU AGURAWARU ,  KAPIRU SHIYANKAA ,  FUARASU ENU MUBARAKU

    IPC: G01R31/3185 ,  G06F7/00 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To improve design flexibility by providing a programmable means which responds to a logic circuit output and generates an output signal, responds to an output enabling signal and connects the output signal to a data node and selects which logic state connects the output signal to the data node. SOLUTION: A programmable AND array 22 uses another combination of logic cells and a product-sum mechanism. A logic signal of a line 24 is given as a combination signal of a product-sum term to OR gates 26, 46 and 74. A common synchronous preset signal and a common asynchronous reset signal are given to an output register part 16 of a PLA device 10, an output micro cell 18 and a register of a buried register part 20. The common preset signal is given as a product term from an output of a programmable AND array 22 to a line 29b. The function of the device 10 is improved by a control signal that is given to a field programmable fuse 32, etc.

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