公开(公告)号：JPH096713A

公开(公告)日：1997-01-10

申请号：JP15016595

申请日：1995-06-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BIKUTAA EFU ANDOREEDO ,  KERII EMU HOOTON

IPC: G06F13/16 ,  G06F13/28

Abstract: PURPOSE: To provide a system for optimizing data transfer time between an external master device and a main memory. CONSTITUTION: The system includes an integrated processor provided with a PCT bridge 80 for adjusting data transfer to/from a PCT master 75 and a memory controller 90 for controlling an access to the main memory. When the PCI master 75 can not timely respond, the bridge 80 asserts a MEMWAIT signal to the controller 90 to indicate the necessity of deceleration of data transfer, applies a succeeding memory address to open a proper page in the memory and asserts a suitable row address strobe line to accelerate succeeding data transfer. When the MEMWAIT signal is deasserted, the controller 90 immediately asserts a column address strobe line to drive data. Since the page in the memory is quickly opened, RAS access time and RAS precharging time can be saved.

公开(公告)号：JPH07152449A

公开(公告)日：1995-06-16

申请号：JP22433694

申请日：1994-09-20

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DAGURASU DEII GEFUAATO ,  KERII EMU HOOTON ,  RITA OBURAIEN ,  JIEIMUZU AARU MAKUDONARUDO

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/32 ,  G06F13/364

Abstract: PURPOSE: To provide a system and a method for controlling peripheral bus clock signals. CONSTITUTION: Before the stoppage of the peripheral bus clock signals, indicator signals are generated by a clock control circuit (120). A slave device generates clock request signals when the peripheral bus clock signals are kept requested. The clock control circuit receives them and prevents the peripheral bus clock signals from being stopped. When an alternate bus master (108; 110) requires the control of a peripheral bus (102) in stopping the peripheral bus clock signals, the alternate bus master can be constituted so as to assert the clock request signals for the restart of the peripheral bus clocks. The signals are sent to the peripheral bus and the clock control circuit receives them and restarts the peripheral bus clock signals. The alternate bus master can generate bus request signals synchronized with the peripheral bus clock signals so as to obtain enabling signals from a bus arbiter unit (106).