公开(公告)号：JPH04333279A

公开(公告)日：1992-11-20

申请号：JP34451391

申请日：1991-12-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KIANOOSHIYU NASHINEE

IPC: H01L27/092 ,  H01L21/8238 ,  H03K19/003

Abstract: PURPOSE: To provide a CMOS output buffer circuit which enables substantial reduction of ground return. CONSTITUTION: This CMOS output buffer circuit for supplying output signals at an output terminal provided with a substantial reduction of the ground return is provided with a pull-up driver circuit (12), a pull-down driver circuit (14) and a control circuit (16). The pull-up driver circuit is provided with first and second resistance means for delaying the time of turning on a pull-up transistor, and the pull-down driver circuit is provided with third and forth resistance elements for delaying the time of turning for a pull-down transistor. The respective first - fourth resistance elements (D1-D4) are formed from a transmission gate and function, so as to control a gate-source voltage applied to the respective gates of the pull-up and pull-down transistors.

公开(公告)号：JPH05136684A

公开(公告)日：1993-06-01

申请号：JP4982892

申请日：1992-03-06

Applicant: ADVANCED MICRO DEVICES INC

Inventor： KIANOOSHIYU NASHINEE

IPC: H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175

Abstract: PURPOSE: To provide an improved edge speed feedback CMOS output buffer circuit in which induced ringing is considerably reduced. CONSTITUTION: The CMOS output buffer circuit includes an output driver stage 12, a pull-up pre-driver circuit 14, a pull-down predriver circuit 16, and a feedback means. The output driver stage is made up of a pull-up transistor(TR) P1 and a pull-down TR N1. Relating to the feedback means, a rising speed of a voltage is controlled by a gate electrode of the pull-down TR N1 to slow down a time of turn-on when a level of the output terminal transits from a high level to a low level in response to an output signal thereby reducing considerably a rebounding on ground. The feedback means is made up of a capacitor C2 consisting of a 1st plate connecting to the output terminal and a 2nd plate coupled with the gate electrode of the pull-down TR N1.