INTEGRATED CIRCUIT
    1.
    发明专利

    公开(公告)号:JPH11177406A

    公开(公告)日:1999-07-02

    申请号:JP16686398

    申请日:1998-06-15

    Inventor: KUBINEC JAMES J

    Abstract: PROBLEM TO BE SOLVED: To reduce the number of pins by connecting a second filter to a chip function element to constitute a transceiver, exchanging bit data from a power source line to obtain serializing/non-serializing configuration and transferring a signal between chips. SOLUTION: A chip function element 208 of an IC 200 transfers parallel bit data to a transceiver 206 and serializes plural kinds of bit data into a serial data stream. The transceiver 206 outputs it at a high speed, permits it to be a high frequency component with a high-pass filter 204 and transmits it to IC 210 with a power source line Vcc. The high frequency component of the power source line Vcc is extracted by the high-pass filter 214 of IC 210, transmitted to the transceiver 216 to be non-serialized and returned to parallel bit data at the time of transmission. In this way, a serial link is constituted between ICs 200 and 210 with the power source line Vcc. Then, parallel data exchange which is executed conventionally by the plural pins is serially executed through the power source pins and becomes replaceable for a single power source pin.

    2.
    发明专利
    未知

    公开(公告)号:AT114201T

    公开(公告)日:1994-12-15

    申请号:AT89309675

    申请日:1989-09-22

    Inventor: KUBINEC JAMES J

    Abstract: A programmable computer shift register or other time delay means of variable length that provides time delays that are integral multiples of a predetermined time delay unit DELTA t, that uses relatively few switches, that controls time delays introduced by passage of signals through multiple-state switches that are in different states.

    3.
    发明专利
    未知

    公开(公告)号:DE68919401D1

    公开(公告)日:1994-12-22

    申请号:DE68919401

    申请日:1989-09-22

    Inventor: KUBINEC JAMES J

    Abstract: A programmable computer shift register or other time delay means of variable length that provides time delays that are integral multiples of a predetermined time delay unit DELTA t, that uses relatively few switches, that controls time delays introduced by passage of signals through multiple-state switches that are in different states.

    4.
    发明专利
    未知

    公开(公告)号:DE68919401T2

    公开(公告)日:1995-05-04

    申请号:DE68919401

    申请日:1989-09-22

    Inventor: KUBINEC JAMES J

    Abstract: A programmable computer shift register or other time delay means of variable length that provides time delays that are integral multiples of a predetermined time delay unit DELTA t, that uses relatively few switches, that controls time delays introduced by passage of signals through multiple-state switches that are in different states.

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