公开(公告)号：JPH07182163A

公开(公告)日：1995-07-21

申请号：JP26243794

申请日：1994-10-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO BII UITSUTO ,  MAIKERU DEI GODAADO

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455

Abstract: PURPOSE: To provide the method and device which easily improve the performance of a CISC processor. CONSTITUTION: A super-scalar CISC processor 100 having a RISC super-scalar core 110 includes an instruction cache 104, a byte queue 106, and an instruction decoder 108. This decoder 108 includes a logic conversion route, a memory conversion route, and a common conversion route for conversion of a CISC instruction to RISC similar operation ROP in each issue position. An ROP multiplexer sends an x86 instruction from the byte queue 106 to conversion routes, and a selection circuit collects ROP information from proper conversion routes, and a shared circuit processes ROP information from the selection circuit for resources to be shared. An ROP type and op code information are issued from the instruction decoder to the RISC core.

公开(公告)号：JPH08190482A

公开(公告)日：1996-07-23

申请号：JP20876895

申请日：1995-08-16

Applicant: ADVANCED MICRO DEVICES INC

Inventor： NEISAN ERU YAO ,  MAIKERU DEI GODAADO

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/455

Abstract: PROBLEM TO BE SOLVED: To provide the high-speed scanning of the instruction queue of a super scalar processor for appropriately controlling the direction of one or more instructions to the issuing position of the super scalar processor. SOLUTION: A super scalar CISC(complicated instruction set computer) processor 100 provided with an RISC(reduced instruction set computer) super scalar core 110 is provided with an instruction cache 104, a byte queue 106 and an instruction decoder 108. The instruction decoder 108 is provided with a logic base, a memory base and a common conversion route for converting a CISC instruction to a ROP at the respective issuing positions. An ROP multiplexer is provided with scanning logic for sending x86 instructions from the byte queue 106 to the conversion route, generating the array of ROP information signals and a bit for discriminating an op code position at the respective issuing positions and scanning the byte queue 106 at a high speed. The scanning logic is divided into the groups of bit processing logic and is provided with look-ahead ability among the groups.

公开(公告)号：JPH07182162A

公开(公告)日：1995-07-21

申请号：JP26070194

申请日：1994-10-25

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIBITSUDO BII UITSUTO ,  MAIKERU DEI GODAADO

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

Abstract: PURPOSE: To improve processor performance by fetching and dispatching 4 or less X86 instructions in each one clock cycle by using an instruction cache. CONSTITUTION: A processor includes a data cache(DCACHE)32, a second level cache(L2CACHE) 36 for both instructions and data, a memory managing unit(MMU) 38 for both the instructions and data, and a bus interface unit(BIU) 34. A super scalar RISC core can execute four or less ROP in the same clock cycle by four sets of ROP(RISC(composite instruction set computer) analogous operation) dispatch bus 40, A, B pointer bus 42, A, B operand bus 44, and result bus 46. Thus, the performance of an RISC processor is improved.