公开(公告)号：JPH09102199A

公开(公告)日：1997-04-15

申请号：JP10263896

申请日：1996-04-24

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO BII RICHIYAATO ,  NIPENDORA JIEI PATERU ,  SHIYAIAMU JII GAAGU

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To provide a non-volatile memory cell having the array of memory cells of single transistor to be read according to an improved read cycle operation. SOLUTION: Concerning a selected cell 12 to be mutually connected through a single bit line 16 to the other cell, the activity required for identifying the programmed or non-programmed state of that cell 12 is guaranteed. Concerning the non-selected cell to be connected to the selected cell, inactivity is advantageously guaranteed by impressing a negative voltage to a word line 20 related to these cells. This negative voltage is lower than a threshold voltage related to the MOS device of single transistor. Therefore, the non-selected cell is kept inactive and the single active or inactive selected cell usually depending on the programmed state of array is applied. With the negative voltage loaded to the non-selected cell, the leak of over erased cells always related to a depression type operation is minimized.