PROGRAMMABLE LOGIC DEVICE
    1.
    发明专利

    公开(公告)号:JPH04229720A

    公开(公告)日:1992-08-19

    申请号:JP9932191

    申请日:1991-04-30

    Abstract: PURPOSE: To provide a programmable logic device having a delay line which has a programmably selectable tap which sends an input to a programmable logic circuit. CONSTITUTION: The delay line tap gives an input to a programmable logic circuit 20 through a logic circuit drive means 18, and the means executes a preparatory processing of a quantity on the tap signal, before it is given to the programmable logic circuit. The output of the programmable logic circuit, which may be a programmable AND array 20 followed by a fixed OR array 22, is given to the edge trigger input of a dual set/reset flip flop. Other outputs of the programmable logic circuit can be selected as the input to the delay line.

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