公开(公告)号：JPH07303010A

公开(公告)日：1995-11-14

申请号：JP6292995

申请日：1995-03-22

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  MAAKU EI AIRUTON

IPC: H03B28/00 ,  G06F7/548 ,  H03H17/00 ,  H03H17/02

Abstract: PURPOSE: To provide a device and a method for synthesizing sine wave signals generated from plural sampled values picked up during a sampling time of continuous sampling intervals. CONSTITUTION: This device is provided with a 1st logic unit 80 for generating continuous samples of a step value and of a next step value by repeatedly processing an initial step value, and with a 2nd logic units 90, 92, 94 and 104 for repeatedly generating next parameter values. A 2nd logic unit receives continuous samples of step values, repeatedly generates the continuous samples of temporary parameter values and derivative temporary parameter values, generates next parameter values by repeatedly processing these samples and continuously, repeatedly generates the parameter values upto the end of a time interval or until a specified parameter value becomes practically equal to a 2nd parameter value.

公开(公告)号：JPH03209935A

公开(公告)日：1991-09-12

申请号：JP29165190

申请日：1990-10-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  JIYON JII BAATOKOUIAKU

IPC: H03M1/00 ,  G06F3/05 ,  H03H17/02 ,  H03H17/06 ,  H04B14/04

Abstract: PURPOSE: To provide an adapted device by providing a signal processing circuit for decimating a signal from A/D conversion and giving it to a digital device and for interpolating the outputted digital signal and giving it to D/A conversion. CONSTITUTION: An analog-digital-analog circuit 14 receives an inputted analog signal by a line 16 from an analog device 12 and outputs the digital signal outputted to a line 30. The circuit 14 transmits the inputted digital signal to a decimation-interpolation circuit 18 through a line 20 and receives the interpolated digital signal from the circuit 18 through a line 28. The circuit 18 is constituted of a digital input circuit 66, a first digital cell circuit 68, second digital cell circuits 79 and 72 and an output circuit 92. The circuit is constituted of a shift register RO receiving input from a multiplexer 74 and giving output to one bit adder SA, of a multiplexer 96 and a shift register R1B. The output of a programmable logic array 78 is given to the shift register R1B through a line 100.

公开(公告)号：JPH03179941A

公开(公告)日：1991-08-05

申请号：JP29164990

申请日：1990-10-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  JIYON JII BAATOKOUIAKU

IPC: H03M1/12 ,  G06F3/05 ,  H03H17/06 ,  H04B14/04

Abstract: PURPOSE: To save labor for engineering design and to attain the manufacturing of the device by providing the device with a digital signal processing circuit for decimating an incoming digital signal and constituting the digital signal processing circuit so as to allow a specified set of plural modules to repeat decimation for a specified number of times. CONSTITUTION: An analog/digital(A/D) circuit 14 converts an incoming analog signal received by a line 16 into a digital signal and transmits the digital signal to a decimation circuit 18. The circuit 18 applies decimation operation to the inputted digital signal and outpours a decimated digital signal. The circuit 18 consists of a decimator module 19 and an output circuit 92. An additional decimator module 19a may be added to execute decimation furthermore as necessity. The module 19 consists of a digital input circuit 66, a 1st digital cell circuit 68 and 2nd digital cell circuits 70, 72, 73. The 2nd digital cell circuits may be added to the decimator module 19 as necessity.

公开(公告)号：JPH0738509A

公开(公告)日：1995-02-07

申请号：JP16597291

申请日：1991-07-05

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  JIYON JII BAATOKOBIAKU

IPC: G06F15/16 ,  G06F9/38 ,  G06F15/177 ,  G06F15/78 ,  G10L19/00 ,  G10L19/08 ,  G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B7/085 ,  G11B11/105 ,  G11B19/247 ,  H04B14/04 ,  G10L9/14 ,  G10L9/18

Abstract: PURPOSE: To attain a concentrical digital signal processing algorithm by using a conventionally available component element that operates at a conventional clock speed. CONSTITUTION: A single integrated circuit chip contains a CPU 200 which includes an execution device having an arithmetic and logic unit and an accumulator, a program counter, a memory, a clock generator, a timer, a bus interface, a chip selection/output device and an interrupt processor, a digital signal processor(DSP) 300 which includes an instruction set that executes the digital signal processing algorithm, an execution device that executes the multiplication and accumulation functions and an external interface, and a combination of an address bus 102 connected between the CPU 200 and the DSP 300, a data bus 104 connected between the CPU 200 and the DSP 300 and a static scheduler which statically executes the signal processing algorithm between the CPU 200 and the DSP 300.

公开(公告)号：JPH03179942A

公开(公告)日：1991-08-05

申请号：JP29165090

申请日：1990-10-29

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA EMU ASUGAA ,  JIYON JII BAATOKOUIAKU

IPC: H03M1/66 ,  G06F17/17 ,  G06J1/00 ,  H04B14/04

Abstract: PURPOSE: To save labor for engineering setting and to attain its manufacturing by providing the device with a digital signal processing circuit for outputting an interpolated digital signal and constituting the digital signal processing circuit so as to allow a specified set of plural modules to repeat interpolation by the specified number of times. CONSTITUTION: A digital device 24 applies an outgoing digital signal to an interpolation circuit 18 through a line 26. The circuit 18 executes interpolating operation for the output digital signal received through the line 26 and outputs an interpolated digital signal to a digital/analog(D/A) circuit 14 through a line 28. The circuit 18 consists of an interpolator module 19 and an output circuit 92. An additional interpolator module 19a may be added to execute additional interpolation as necessity. The module 19 consists of a 1st digital circuit 68 and 2nd digital cell circuits 70, 72, 73. Second digital cell circuits may be added to the module 19 to execute interpolation of a larger degree as necessity.