公开(公告)号：JPH07211811A

公开(公告)日：1995-08-11

申请号：JP30604394

申请日：1994-12-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO BII RICHIYAATO ,  SHIYAMU JII GAAGU ,  FUEI WAN

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a method for manufacturing a monolithic integrated circuit comprising a flash EPROM device. CONSTITUTION: An array 12 and a self-alignment source region in a redundancy select area 20 are, for opening a self-alignment source region and also for direct implantation of phosphorous of a small dose to a silicon substrate bellow it, provided with a single mask. A careful control and removal, thereafter, of the residue in an etched region through wet-etching is helpful for an implantation edge to be anisotropically controlled and separated with sure for lateral diffusion/drive-in thereafter. Thus, the flash EPROM device of a plurality of transistors in the array and the redundancy select area is process-controlled, thus significant reduction is provided in threshold skewing.

公开(公告)号：JPH07221210A

公开(公告)日：1995-08-18

申请号：JP30622394

申请日：1994-12-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO BII RICHIYAATO ,  SHIYAMU JII GAAGU ,  BURATSUDOREE TEII MUUA JIYUNIA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a non-volatile memory array having a self-aligned interpoly dielectric between a stacked pair of polysilicon strips. CONSTITUTION: In order to provide a good bonding between polysilicon strips and insure no deposition of nay additional oxides while a bit line oxide 80 is formed on a vertual ground bit line diffusion section, a self-aligned interpolydielectric 76 is aligned with edges of the stacked polysilicon strips. In the manufacturing process, there is no necessity of removing the self-aligned interpoly dielectric 76 and therefore an additional heat cycle which is necessary for removing additional (or replacement) dielectrics and reproducing new ones is not required. Accordingly a wet oxide 80 is placed at the polysilicon/silicon- oxide interface to enhance a data retention of a floating polysilicon 30a and minimize a thermal cycle and a short-channel effects associated therewith and thereafter, a dry oxide 82 is formed.

公开(公告)号：JPH07202049A

公开(公告)日：1995-08-04

申请号：JP30584094

申请日：1994-12-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： ROBAATO BII RICHIYAATO ,  SHIYAMU JII GAAGU ,  BURATSUDOREE TEII MUUA JIYUNIA

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a MOS device which has the implant into its channel region from its drain or the source side in order to minimize its short-channel effects. CONSTITUTION: Implant into the channel region of a MOS device is achieved by a conventional process technique, wherein the direction of a channel implant is substantially vertical with respect to the upper surface of a substrate. Numerous masking steps and reorientation of the substrate of the MOS device are not required. Further, the implant masks of its drain side or source side can be formed out of an existing mask and the implant into its channel region can be integrated into the flow of a standard processing for either standard MOS device or memory array, including double polysilicon. When selecting the implant into the channel region from its drain side, a boundary line 56 between its drain implant region and its substrate which are arranged laterally is disposed preferably in the interior of its channel region, and is disposed preferably near the intermediate point of its channel as being separated downward by a distance from a polysilicon 55 provided on its cannel.