公开(公告)号：JPH03105791A

公开(公告)日：1991-05-02

申请号：JP23690990

申请日：1990-09-05

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIMII FUAN ,  JIU AN ,  DEIBITSUDO ERU KIYANBURU ,  SUTEIIBUN SHIYUYU

IPC: G11C11/413 ,  G06F5/10 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  H03K3/037

Abstract: PURPOSE: To allow a same circuit to be used both on a high power impression and a low power impression by providing a COMS(complimentary MOS) pipe line memory address buffer having a selective changeover means between an asynchronous operation and a synchronous operation of a buffer. CONSTITUTION: A buffer has a first and a second bus gates 21 and 22, and the bus gates 21 and 22 have individually a pair of complementary MOS(CMOS) transistors P21, N21 and P22, N22, and the buffer 20 is selectively changed over between the asynchronous mode and the synchronous mode in the operation. Further, this circuit is provided with a first means 31, 32 of alternately opening/closing the bus gates 21 and 22 when the buffer operates in synchronous mode, and a second means 33, 34 for simultaneously opening both bus gates 21 and 22 when the buffer operates in asynchronous mode. Consequently, a same circuit can be used both on high power impression and a low power impression.