OUTPUT BUFFER CIRCUIT
    1.
    发明专利

    公开(公告)号:JPH0773687A

    公开(公告)日:1995-03-17

    申请号:JP13431094

    申请日:1994-06-16

    Abstract: PURPOSE: To obtain an output buffer circuit programmable using a standard programmer in a high voltage although it is operated with an applied low voltage. CONSTITUTION: A program verifying logic signal from a programmer is detected with the output buffer circuit 10, and the speed of output driver transistors 12, 14 is reduced with a device speed reducing block 11 when the signal is detected. Whereby, a noise problem due to a higher voltage in programming of an EPROM device is excluded, at the same time, the output buffer circuit 10 is operated at a required performance level during the normal operation.

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