公开(公告)号：JPS6470832A

公开(公告)日：1989-03-16

申请号：JP17620688

申请日：1988-07-13

Applicant: ADVANCED MICRO DEVICES INC

Inventor： TEIMOSHII EE ORUSON ,  DAAWARU AJIYUMEERAA

IPC: G06F9/34 ,  G06F5/16 ,  G06F12/04 ,  G06F12/06

Abstract: PURPOSE: To buffer a variable length data word in one clock cycle by providing plural FIFOs, an input/output data bus connected thereto, and input/output rotators, and also providing a logic circuit which is supplied with a control signal and a pointer. CONSTITUTION: Four first-in first-out random access memories(FIFO) 0-3 and two rotators 1 and 9 are used. The rotators can process 1-byte to 4-byte variable length data words at a time. The variable length words consisting of 1-4 types can be queued and dequeued by enabling FIFO buffering and FIFO buffering using the painter 7. The bytes are rotated by the rotators, the FIFO buffering is enabled individually, and the control signal indicating the storage place of an active state is generated by a logic circuit.