公开(公告)号：EP1344221A2

公开(公告)日：2003-09-17

申请号：EP01959389.6

申请日：2001-07-31

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： AKAOGI, Takao ,  AL-SHAMMA, Ali ,  KIM, Yong ,  CLEVELAND, Lee ,  LIN, Jin-Lien ,  NGUYEN, Kendra ,  TEH, Boon Tang

IPC: G11C8/08 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A flash memory (100) having word line decoding and selection architecture is described. The flash memory include first (202, 204) and second (206, 208) sectors of memory cells, first (201, 212) and second (214, 216) local driver circuits, first (218), second (222, 224) and third (226, 228) decoding circuits, and a driving circuit (220). A first side of decoding circuitry (218) activates a first selected plurality of local driver circuits (210, 212) and a second side of decoding circuitry (218) activates a second selected plurality of local driver circuits (214, 216). The second decoding circuits (222, 224) are coupled to the first local driver circuit. The third decoding circuits (226, 228) are coupled to the second local driver circuits (214, 216) and supply a second boosted voltage to the second selected word line. The driving circuit (220) supplies boosted voltages to the first, second and third decoding circuites (218, 22, 224, 226, 228) and the first and second local river circuits (210, 212, 214, 216).

公开(公告)号：EP1327193B1

公开(公告)日：2007-02-21

申请号：EP01953538.4

申请日：2001-07-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  FASL LLC

Inventor： AL-SHAMMA, Ali ,  AKAOGI, Takao

IPC: G06F11/20

CPC classification number: G11C16/26 ,  G11C15/00 ,  G11C15/046

Abstract: A device for performing redundant reading in a flash memory. The device includes arrays of regular memory cells (410) and arrays of redundant memory cells (412). Some of the regular memory cells may have defective addresses. A regular sense amplifier (420) will read the regular memory cells at their accessed address while a redundant sense amplifier (422) will read the redundant memory cells. A first array (432) of CAMs will store the defective addresses of the defective memory cells while a second array (432) of CAMs will store the input/output designators of the defective memory cells. Decoding circuitry (460) will decode the input/output designators of both the defective and non-defective memory cells A multi-bit multiplexer stage (490) will output either the contents of the regular memory cell (410) or, if the address is defective, the contents of the redundant memory cell (412). The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.

公开(公告)号：EP1290559B1

公开(公告)日：2004-03-24

申请号：EP01939217.4

申请日：2001-05-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AL-SHAMMA, Ali ,  CLEVELAND, Lee

IPC: G06F11/20 ,  G11C8/16 ,  G11C15/04

CPC classification number: G11C29/789 ,  G11C8/16 ,  G11C15/046

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry (106) is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array (118, 120, 122, 124, 134, 136, 138, 140) of memory cells, a redundant array (126, 128, 130, 132, 142, 144, 146, 148) of memory cells, and the redundancy CAM circuitry (106). The redundancy CAM circuitry (106) includes a plurality of dual-ported CAM stages (200). Each CAM stage (200) includes a CAM cell (202), a write data bus (204) coupled to the CAM cell (202), and a read data bus (206) coupled to the CAM cell (202). The CAM cell (202) stores information regarding a location of an inoperative memory cell in the primary array (118, 120, 122, 124, 134, 138, 140). The inoperative memory cell requires a substitution with a second memory cell in the redundant array (126, 128, 130, 132, 142, 144, 146, 148). The write data bus (204) produces the information from the CAM cell (202) responsively to a write select signal (WSELm). The write select signal (WSELm) is indicative of a write operation to be performed at memory cell locations in the primary array (18, 120, 122, 124, 134, 136, 138, 140). The read data bus (206) produces the information from the CAM cell (202) responsively to a read select signal (RSELm). The read select signal (RSELm) is indicative of a read operation to be performed at memory cell locations in the primary array (118, 120, 122, 124, 134, 136, 138, 140).

公开(公告)号：EP1327193A2

公开(公告)日：2003-07-16

申请号：EP01953538.4

申请日：2001-07-17

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： AL-SHAMMA, Ali ,  AKAOGI, Takao

IPC: G06F11/20

CPC classification number: G11C16/26 ,  G11C15/00 ,  G11C15/046

Abstract: A device for performing redundant reading in a flash memory. The device includes arrays of regular memory cells (410) and arrays of redundant memory cells (412). Some of the regular memory cells may have defective addresses. A regular sense amplifier (420) will read the regular memory cells at their accessed address while a redundant sense amplifier (422) will read the redundant memory cells. A first array (432) of CAMs will store the defective addresses of the defective memory cells while a second array (432) of CAMs will store the input/output designators of the defective memory cells. Decoding circuitry (460) will decode the input/output designators of both the defective and non-defective memory cells A multi-bit multiplexer stage (490) will output either the contents of the regular memory cell (410) or, if the address is defective, the contents of the redundant memory cell (412). The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.

公开(公告)号：EP1290559A2

公开(公告)日：2003-03-12

申请号：EP01939217.4

申请日：2001-05-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AL-SHAMMA, Ali ,  CLEVELAND, Lee

IPC: G06F11/20

CPC classification number: G11C29/789 ,  G11C8/16 ,  G11C15/046

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry (106) is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array (118, 120, 122, 124, 134, 136, 138, 140) of memory cells, a redundant array (126, 128, 130, 132, 142, 144, 146, 148) of memory cells, and the redundancy CAM circuitry (106). The redundancy CAM circuitry (106) includes a plurality of dual-ported CAM stages (200). Each CAM stage (200) includes a CAM cell (202), a write data bus (204) coupled to the CAM cell (202), and a read data bus (206) coupled to the CAM cell (202). The CAM cell (202) stores information regarding a location of an inoperative memory cell in the primary array (118, 120, 122, 124, 134, 138, 140). The inoperative memory cell requires a substitution with a second memory cell in the redundant array (126, 128, 130, 132, 142, 144, 146, 148). The write data bus (204) produces the information from the CAM cell (202) responsively to a write select signal (WSELm). The write select signal (WSELm) is indicative of a write operation to be performed at memory cell locations in the primary array (18, 120, 122, 124, 134, 136, 138, 140). The read data bus (206) produces the information from the CAM cell (202) responsively to a read select signal (RSELm). The read select signal (RSELm) is indicative of a read operation to be performed at memory cell locations in the primary array (118, 120, 122, 124, 134, 136, 138, 140).