TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
    1.
    发明授权
    TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE 有权
    电路及方法微调,字线驱动器和最小化生产相关的各种变化INCREASED字线电压

    公开(公告)号:EP1266382B1

    公开(公告)日:2004-01-02

    申请号:EP01910464.5

    申请日:2001-02-07

    CPC classification number: G11C16/08 G11C5/145 G11C8/08

    Abstract: A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory (10) is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster (48) in a wordline voltage booster circuit (20). An adjustable clamp circuit (12) is electrically connected with the wordline voltage booster circuit (20) for clamping the gate voltage that is generated by the voltage booster (48) at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit (14) that is electrically connected to the adjustable clamp circuit (12), depending on process variations experienced during fabrication by the adjustable clamp circuit (12).

    TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
    2.
    发明公开
    TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE 有权
    电路及方法微调,字线驱动器和最小化生产相关的各种变化INCREASED字线电压

    公开(公告)号:EP1266382A1

    公开(公告)日:2002-12-18

    申请号:EP01910464.5

    申请日:2001-02-07

    CPC classification number: G11C16/08 G11C5/145 G11C8/08

    Abstract: A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory (10) is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster (48) in a wordline voltage booster circuit (20). An adjustable clamp circuit (12) is electrically connected with the wordline voltage booster circuit (20) for clamping the gate voltage that is generated by the voltage booster (48) at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit (14) that is electrically connected to the adjustable clamp circuit (12), depending on process variations experienced during fabrication by the adjustable clamp circuit (12).

    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT
    3.
    发明授权
    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT 有权
    的闪存架构使用复合式金属连接

    公开(公告)号:EP1256116B1

    公开(公告)日:2003-09-03

    申请号:EP00948688.7

    申请日:2000-07-14

    CPC classification number: G11C8/12 G11C8/10

    Abstract: The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.

    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT
    4.
    发明公开
    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT 有权
    的闪存架构使用复合式金属连接

    公开(公告)号:EP1256116A2

    公开(公告)日:2002-11-13

    申请号:EP00948688.7

    申请日:2000-07-14

    CPC classification number: G11C8/12 G11C8/10

    Abstract: The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.

    WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM)
    5.
    发明授权
    WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) 有权
    字线驱动器对于快闪EEPROM

    公开(公告)号:EP1116240B1

    公开(公告)日:2002-11-13

    申请号:EP99949746.4

    申请日:1999-09-21

    CPC classification number: G11C16/08 G11C8/08

    Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) (10) includes a plurality of floating gate transistor memory cells (32), a plurality of wordlines (WL) connected to the cells (32) and a power source (13) for generating a low power supply voltage on the order of 3 V or less. A wordline driver (50) includes a booster (52) for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp (54) limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp (54) can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp (56) limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the begining of the read operation to ensure that the cells (32) have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

    WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM)
    6.
    发明公开
    WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) 有权
    字线驱动器对于快闪EEPROM

    公开(公告)号:EP1116240A1

    公开(公告)日:2001-07-18

    申请号:EP99949746.4

    申请日:1999-09-21

    CPC classification number: G11C16/08 G11C8/08

    Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) (10) includes a plurality of floating gate transistor memory cells (32), a plurality of wordlines (WL) connected to the cells (32) and a power source (13) for generating a low power supply voltage on the order of 3 V or less. A wordline driver (50) includes a booster (52) for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp (54) limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp (54) can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value. A lower clamp (56) limits the wordline voltage to a minimum value which is higher than the supply voltage and lower than the maximum value for a predetermined length of time at the begining of the read operation to ensure that the cells (32) have sufficient read current and to reduce the amount by which the minimum value varies with the supply voltage.

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