公开(公告)号：WO2002080181A2

公开(公告)日：2002-10-10

申请号：PCT/US2001/043543

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： BAUTISTA, Edward, V., Jr. ,  KURIHARA, Kazuhiro ,  PAN, Feng ,  LEE, Weng, Fook ,  SUNKAVALLI, Ravi ,  HAMILTON, Darlene

IPC: G11C16/00

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/344

Abstract: A system (10a) is provided for reducing band-to-band tunneling current during flash memory erase operations. The system (10a) includes an I/O memory sector (20) divided into (N) subsectors, N being an integer, and a drain pump (40) to generate power for associated erase operations within the N subsectors. An erase sequencing subsystem (60) generates N pulses to enable the erase operations within each of the N subsectors in order to reduce band-to-band tunneling current provided by the drain pump (40).

Abstract translation: 提供了一种系统（10a），用于在闪速存储器擦除操作期间减少带内隧穿电流。 系统（10a）包括划分为（N）个子部分的N个整数的I / O存储器扇区（20）和用于在N个子部门内产生用于相关联的擦除操作的功率的排水泵（40）。 擦除排序子系统（60）产生N个脉冲，以便能够在N个子部门的每一个内进行擦除操作，以便减少由排水泵（40）提供的带间隧穿电流。

公开(公告)号：EP1264315B1

公开(公告)日：2003-09-10

申请号：EP01920327.2

申请日：2001-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PAN, Feng ,  BILL, Colin, S.

IPC: G11C29/00 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3454

Abstract: A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch (14) is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch (16) is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator (18) is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.

公开(公告)号：EP1264315A2

公开(公告)日：2002-12-11

申请号：EP01920327.2

申请日：2001-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PAN, Feng ,  BILL, Colin, S.

IPC: G11C29/00 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3454

Abstract: A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch (14) is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch (16) is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator (18) is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.