公开(公告)号：WO2003083934A1

公开(公告)日：2003-10-09

申请号：PCT/US2002/040213

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FUSELIER, Mark, B. ,  WRISTERS, Derick, J. ,  WEI, Andy, C.

IPC: H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/26533 ,  H01L21/76243 ,  H01L29/78648

Abstract: The present invention is generally directed to a semiconductor device formed over a multiple thickness buried oxide layer 20, and various methods of making same. In one illustrative embodiment, the device comprises a bulk substrate 12, a multiple thickness buried oxide layer 20 formed above the bulk substrate 12, and an active layer 21 formed above the multiple thickness buried oxide layer 20, the semiconductor device being formed in the active layer 21 above the multiple thickness buried oxide layer 20. In some embodiments, the multiple thickness buried oxide layer 20 is comprised of a first section 20B positioned between two second sections 20A, the first section 20B having a thickness that is less than the thickness of the second sections 20A. In one illustrative embodiment, the method comprises performing a first oxygen ion implant process 42 on a silicon substrate 40, forming a masking layer 44 above the substrate 40, performing a second oxygen ion implant process 46 on the substrate 40 through the masking layer 44, and performing at least one heating process on the substrate 40 to form a multiple thickness buried oxide layer 20 in the substrate 40. In another illustrative embodiment, the method comprises performing a first oxygen ion implant process 46 on a silicon substrate 40, forming a masking layer 44 above the substrate 40, performing a second oxygen ion implant process 42 on the substrate through the masking layer 44, and performing at least one heating process on the substrate 40 to form a multiple thickness buried oxide layer 20 in the substrate 40. In yet another illustrative embodiment, the method comprises forming a multiple thickness buried oxide layer 20 using a wafer bonding technique.

Abstract translation: 本发明一般涉及形成在多层掩埋氧化物层20上的半导体器件及其制造方法。 在一个说明性实施例中，该器件包括块状衬底12，形成在本体衬底12上方的多层掩埋氧化物层20和形成在多层掩埋氧化物层20上方的有源层21，该半导体器件形成于活性层 在一些实施例中，多层厚度掩埋氧化物层20由位于两个第二部分20A之间的第一部分20B组成，第一部分20B的厚度小于 第二部分20A。 在一个说明性实施例中，该方法包括在硅衬底40上执行第一氧离子注入工艺42，在衬底40上方形成掩模层44，通过掩模层44在衬底40上执行第二氧离子注入工艺46， 以及在衬底40上执行至少一个加热过程，以在衬底40中形成多层掩埋氧化物层20.在另一示例性实施例中，该方法包括在硅衬底40上执行第一氧离子注入工艺46，形成掩模 在衬底40上方的层44，通过掩模层44在衬底上执行第二氧离子注入工艺42，并且在衬底40上执行至少一个加热过程，以在衬底40中形成多层掩埋氧化物层20。 另一个说明性实施例，该方法包括使用晶片接合技术形成多层掩埋氧化物层20。

公开(公告)号：WO1998002917A1

公开(公告)日：1998-01-22

申请号：PCT/US1997004991

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/7835

Abstract: The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the gate material overlying a first region of the semiconductor substrate is removed forming a first sidewall of a gate electrode. A dopant is implanted into the first region after forming the first sidewall. After the first region is implanted, a second portion of the gate material overlying a second region of the semiconductor substrate is then removed forming a second sidewall of the gate electrode. A dopant is implanted into the second region after forming the second sidewall. Spacers are formed adjacent to each of the sidewalls of the gate electrode. Then, a dopant is implanted into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers. In one embodiment of the invention, the first region is a heavily doped source region and the second region is a lightly doped drain region. In another embodiment of the present invention the first region is a lightly doped drain region and the second region is a heavily doped source region. In both embodiments, a part of the lightly doped drain region is retained beneath a spacer.

Abstract translation: 本发明的非对称IGFET的制造方法包括提供具有绝缘膜和栅极材料的半导体衬底。 去除覆盖半导体衬底的第一区域的栅极材料的第一部分，形成栅电极的第一侧壁。 在形成第一侧壁之后，将掺杂剂注入第一区域。 在植入第一区域之后，然后移除覆盖半导体衬底的第二区域的栅极材料的第二部分，形成栅电极的第二侧壁。 在形成第二侧壁之后，将掺杂剂注入第二区域。 隔板与栅电极的每个侧壁相邻形成。 然后，将掺杂剂注入到半导体衬底的第一和第二区域的位于栅电极和间隔物外部的部分中。 在本发明的一个实施例中，第一区域是重掺杂的源极区域，而第二区域是轻掺杂的漏极区域。 在本发明的另一个实施例中，第一区域是轻掺杂漏极区域，第二区域是重掺杂源极区域。 在两个实施例中，轻掺杂漏极区的一部分保持在间隔物的下方。

公开(公告)号：WO2004040619A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/032770

申请日：2003-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick, J. ,  XIANG, Qi ,  BULLER, James, F.

IPC: H01L

CPC classification number: H01L29/78696 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/78603

Abstract: A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material (22) is formed on a SOI semiconductor substrate (20) to induce strain in the overlying silicon layer (21). The compressive materials include silicon oxynitride, phosphorus, silicon nitride, and boron/phosphorus doped silica glass.

Abstract translation: 半导体器件具有绝缘体上硅（SOI）和应变硅技术的高速能力，而不需要形成硅锗层。 在SOI半导体衬底（20）上形成一层压缩材料（22），以在上层硅层（21）中引起应变。 压缩材料包括氮氧化硅，磷，氮化硅和硼/磷掺杂石英玻璃。

公开(公告)号：WO2003105232A1

公开(公告)日：2003-12-18

申请号：PCT/US2003/017918

申请日：2003-05-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WRISTERS, Derick, J. ,  WEI, Andy, C. ,  FUSELIER, Mark, B.

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate (30) comprises of an active layer (30C), a buried insulation layer (30B) and a bulk substrate (30A), forming a doped region (34) in the bulk substrate (30A) under the active layer, forming a plurality of transistors (32) above the SOI substrate in an area above the doped region (34) and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product (64), the integrated circuit product being comprised of a plurality of transistors (32) formed in an active layer (30C) of an SOI substrate (30) above a doped region (34) formed in a bulk substrate (30A) of the SOI substrate, the doped region (34) being formed under the active layer, sensing an activity level of the integrated circuit product (64) and applying a voltage of magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product (64).

Abstract translation: 在一个说明性实施例中，该方法包括提供包括有源层（30C），掩埋绝缘层（30B）和本体衬底（30A）的SOI衬底（30），在体衬底中形成掺杂区域（34） （30A），在所述有源层下方，在所述SOI衬底上方的所述掺杂区域（34）上方的区域中形成多个晶体管（32），并向所述掺杂区域施加电压以改变所述多个晶体管中的至少一个的阈值电压 的晶体管。 在另一示例性实施例中，该方法包括提供由至少一个集成电路产品（64）组成的消费产品，所述集成电路产品由形成在SOI衬底的有源层（30C）中的多个晶体管（32）组成 （30），形成在所述SOI衬底的本体衬底（30A）中的掺杂区域（34）上，所述掺杂区域（34）形成在所述有源层下方，感测所述集成电路产品（64）的活动水平并施加 与掺杂区域的电压和极性电压，施加电压的幅度和极性基于感测到的集成电路产品（64）的活动水平来确定。

公开(公告)号：WO2003103040A2

公开(公告)日：2003-12-11

申请号：PCT/US2003/017917

申请日：2003-05-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

IPC: H01L21/762

CPC classification number: H01L29/66772 ,  H01L29/78603

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of a bulk substrate, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having a protective layer 34A formed thereabove, and forming a plurality of dielectric regions 45 in the bulk substrate 30 after the gate electrode 34 is formed, the dielectric regions 45 being self-aligned with respect to the gate electrode 34, the dielectric regions 45 having a dielectric constant that is less than a dielectric constant of the bulk substrate 30A. In further embodiments, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of bulk substrate 30A, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having the protective layer 34A formed thereabove, performing at least one oxygen implant process after the gate electrode 34 and the protective layer 34A are formed to introduce oxygen atoms into the bulk substrate 30A to thereby form a plurality of oxygen-doped regions 52 in the bulk substrate 30A, and performing at least one anneal process to convert the oxygen-doped regions 52 to dielectric regions 45 comprised of silicon dioxide in the bulk substrate 30A. In one illustrative embodiment, the device comprises a gate electrode 34 formed above an SOI structure 30 comprised of a bulk substrate 30A, a buried insulation layer 30B, and an active layer 30C, and a plurality of dielectric regions 45 comprised of silicon dioxide formed in the bulk substrate 30A, the dielectric regions 45 being self-aligned with respect to the gate electrode 34.

Abstract translation: 在一个说明性实施例中，该方法包括在由体基板，掩埋绝缘层30B和有源层30C组成的SOI衬底30上方形成栅电极34，栅电极34具有形成在其上的保护层34A，并形成 形成栅电极34之后的体基板30中的多个电介质区域45，电介质区域45相对于栅电极34自对准，介电区域45的介电常数小于介电常数 体基板30A。 在另外的实施例中，该方法包括在由本体衬底30A，掩埋绝缘层30B和有源层30C组成的SOI衬底30上方形成栅电极34，其上形成有保护层34A的栅电极34执行至少一个 形成栅电极34和保护层34A之后的氧注入工艺，以将氧原子引入本体衬底30A中，从而在本体衬底30A中形成多个氧掺杂区52，并进行至少一个退火工艺以转换 氧掺杂区域52到主体衬底30A中由二氧化硅组成的电介质区域45。 在一个说明性实施例中，该器件包括形成在SOI结构30上方的栅电极34，SOI结构30由体基板30A，掩埋绝缘层30B和有源层30C组成，以及由二氧化硅组成的多个介电区45 本体衬底30A，电介质区域45相对于栅电极34自对准。

公开(公告)号：WO2003096430A1

公开(公告)日：2003-11-20

申请号：PCT/US2002/040272

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FUSELIER, Mark, B. ,  WRISTERS, Derick, J. ,  WEI, Andy, C.

IPC: H01L29/786

CPC classification number: H01L29/78648 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609

Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate (30) comprised of an active layer (30C), a buried insulation layer (30B) and a bulk substrate (30A), the active layer (30C) being doped with a first type of dopant material, the bulk substrate (30A) having an inner well (52) formed therein adjacent a surface of the bulk substrate (30A) and under the active layer (30C), the inner well (52) being doped with the first type of dopant material, forming a transistor (32) above the SOI substrate in an area above the inner well (52) and applying a voltage to the inner well (52) to vary a threshold voltage of the transistor. In some embodiments, the method further comprises forming an NMOS transistor. In other embodiments, the method further comprises forming a PMOS transistor. In another embodiment the magnitude and polarity of an applied voltage being determined based upon a sensed activity level of an integrated circuit product.

Abstract translation: 在一个说明性实施例中，该方法包括提供由有源层（30C），掩埋绝缘层（30B）和体基板（30A）组成的SOI衬底（30），所述有源层（30C）掺杂有第一 类型的掺杂剂材料，所述块体衬底（30A）具有形成在其中的与所述本体衬底（30A）的表面相邻并在有源层（30C）下方的内阱（52），所述内阱（52）掺杂有所述第一 类型的掺杂剂材料，在所述内部阱（52）上方的区域中在所述SOI衬底上方形成晶体管（32），并向所述内部阱（52）施加电压以改变所述晶体管的阈值电压。 在一些实施例中，该方法还包括形成NMOS晶体管。 在其他实施例中，该方法还包括形成PMOS晶体管。 在另一个实施例中，施加电压的大小和极性基于感测到的集成电路产品的活动水平来确定。

公开(公告)号：WO2002071476A3

公开(公告)日：2002-09-12

申请号：PCT/US2002/003945

申请日：2002-02-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PELLERIN, John, G. ,  WRISTERS, Derick, J.

IPC: H01L21/768

Abstract: The integrated circuit device disclosed herein comprises an insulating layer (32) comprised of a first insulating material that has an opening (36) formed therein as defined by at least one sidewall (36A), at least one sidewall spacer (40) positioned adjacent the sidewall (36A) of the opening (36), the sidewall spacer (40) being comprised of a second insulating material, and a conductive interconnection (42) formed in the opening (36) in the insulating layer (32). In a further embodiment, the first insulating material has a dielectric constant less than approximately 3, and a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc. The method disclosed herein comprises forming an opening (36) in a first layer (32) of a first insulating material, the opening (36) being defined by at least one sidewall (36A), and conformally depositing a second layer (38) comprised of a second insulating material in the opening (36) above the sidewall (36A). The method further comprises performing an anisotropic etching process on the second layer to define a sidewall spacer (40) comprised of the second insulating material positioned adjacent the sidewall (36A) of the opening (36), and forming a conductive interconnection (42) in the opening (36) in the insulating layer (32) between the sidewall spacer (40).

公开(公告)号：WO2003103040A3

公开(公告)日：2003-12-11

申请号：PCT/US2003/017917

申请日：2003-05-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

IPC: H01L21/266

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of a bulk substrate, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having a protective layer 34A formed thereabove, and forming a plurality of dielectric regions 45 in the bulk substrate 30 after the gate electrode 34 is formed, the dielectric regions 45 being self-aligned with respect to the gate electrode 34, the dielectric regions 45 having a dielectric constant that is less than a dielectric constant of the bulk substrate 30A. In further embodiments, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of bulk substrate 30A, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having the protective layer 34A formed thereabove, performing at least one oxygen implant process after the gate electrode 34 and the protective layer 34A are formed to introduce oxygen atoms into the bulk substrate 30A to thereby form a plurality of oxygen-doped regions 52 in the bulk substrate 30A, and performing at least one anneal process to convert the oxygen-doped regions 52 to dielectric regions 45 comprised of silicon dioxide in the bulk substrate 30A. In one illustrative embodiment, the device comprises a gate electrode 34 formed above an SOI structure 30 comprised of a bulk substrate 30A, a buried insulation layer 30B, and an active layer 30C, and a plurality of dielectric regions 45 comprised of silicon dioxide formed in the bulk substrate 30A, the dielectric regions 45 being self-aligned with respect to the gate electrode 34.

公开(公告)号：WO2003081678A1

公开(公告)日：2003-10-02

申请号：PCT/US2002/040399

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

IPC: H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate (30A), a buried oxide layer (30B) and an active layer (30C), the transistor being comprised of a gate electrode (36), the bulk substrate (30A) being doped with a dopant material at a first concentration level. The device further comprises a first doped region (42A) formed in the bulk substrate (30A), the first doped region (42A) being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region (42A) is greater than the first dopant concentration level in the bulk substrate (30A), the first doped region (42A) being substantially aligned with the gate electrode (36).

Abstract translation: 本发明一般涉及用于完全耗尽的SOI结构的掺杂方法，以及包括这样得到的掺杂区的器件。 在一个说明性实施例中，器件包括形成在绝缘体上硅衬底上的晶体管，该晶体管由体衬底（30A），掩埋氧化物层（30B）和有源层（30C）组成，晶体管由栅极 电极（36），所述本体衬底（30A）以第一浓度水平掺杂掺杂剂材料。 该器件还包括形成在本体衬底（30A）中的第一掺杂区域（42A），该第一掺杂区域（42A）掺杂与本体衬底掺杂剂材料相同类型的掺杂剂材料，其中， 第一掺杂区域（42A）中的掺杂剂材料大于块状衬底（30A）中的第一掺杂剂浓度水平，第一掺杂区域（42A）基本上与栅电极（36）对准。

公开(公告)号：WO2003081677A1

公开(公告)日：2003-10-02

申请号：PCT/US2002/040398

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

IPC: H01L29/786

CPC classification number: H01L29/78648 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609

Abstract: In one illustrative embodiment, the device comprises a transistor (32) formed above a silicon-on-insulator substrate (30) comprised of a bulk substrate (30A), a buried insulation layer (30B) and an active layer (30C), the bulk substrate (30A) being doped with a first type of dopant material and a first well (50) formed in the bulk substrate (30A), the first well (50) being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well (52) formed in the bulk substrate (30A) within the first material, the transistor (32) being formed in the active layer (30C) above the second well (52) an electrical contact (60) for the first well (50) and an electrical contact (62) for said second well (52). In one illustrative embodiment, a method of forming a transistor (32) above a silicon-on-insulator substrate (30) comprisedof a bulk substrate (30A) a buried oxide layer (30B) and an active layer (30C), the bulk substrate (30A) being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region (50) within the bulk substrate (30A), performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region (52) in the bulk substrate (30A) within the first well (50), the transistor (32) being formed in the active layer (30C) above the second well (52), forming a conductive contact (60) to the first well (50) and forming a conductive contact to the second well (60). The method further comprises a contact well (58) formed in the bulk substrate (30A) within the first well (50), the contact well (58) being comprised of a dopant material that is of the same type as the second type of dopant material, the contact well (58) within the first well (50) having a dopant concentration that is greater than a dopant concentration of the first well (50).

Abstract translation: 在一个说明性实施例中，该器件包括形成在由体衬底（30A），掩埋绝缘层（30B）和有源层（30C）组成的绝缘体上硅衬底上的晶体管（32）， 本体衬底（30A）掺杂有第一类型的掺杂剂材料和形成在本体衬底（30A）中的第一阱（50​​），第一阱（50​​）被掺杂有第二类型的掺杂剂材料 与第一种掺杂剂材料相反。 该器件还包括形成在第一材料内的本体衬底（30A）中的第二阱（52），晶体管（32）形成在第二阱（52）上方的有源层（30C）中，电触点（60） 对于第一井（50）和用于所述第二井（52）的电接触（62）。 在一个说明性实施例中，在由绝缘衬底（30A），掩埋氧化物层（30B）和有源层（30C）组成的绝缘体上硅衬底（30）上方形成晶体管（32）的方法， （30A）被掺杂第一种类型的掺杂剂材料。 该方法包括使用与第一类掺杂剂材料相反的类型的掺杂剂材料来执行第一离子注入工艺，以在本体衬底（30A）内形成第一阱区域（50），使用第二离子注入工艺 掺杂剂材料，其与第一类型的掺杂剂材料相同，以在第一阱（50​​）内的本体衬底（30A）中形成第二阱区（52），晶体管（32）形成在有源层（ 在第二阱（52）上方形成导电接触（60）至第一阱（50​​），并形成与第二阱（60）的导电接触。 该方法还包括形成在第一阱（50​​）内的本体衬底（30A）中的接触阱（58），接触阱（58）由与第二类型的掺杂剂类型相同的掺杂剂材料 第一阱（50​​）内的接触阱（58）具有大于第一阱（50​​）的掺杂剂浓度的掺杂剂浓度。