公开(公告)号：AU2022188A

公开(公告)日：1989-02-02

申请号：AU2022188

申请日：1988-07-29

Applicant: ALLIANT COMPUTER SYSTEMS

Inventor： ZIEGLER MICHAEL L ,  FREDIEU ROBERT L ,  ACHILLES HEATHER D

IPC: G06F12/00 ,  G06F9/52 ,  G06F12/06 ,  G06F12/08 ,  G06F13/18 ,  G06F15/16 ,  G06F15/177

公开(公告)号：AU5893686A

公开(公告)日：1987-01-29

申请号：AU5893686

申请日：1986-06-20

Applicant: ALLIANT COMPUTER SYSTEMS

Inventor： FREDIEU ROBERT L ,  MCANDREW RICHARD T ,  MYSZEWSKI MATHEW J ,  VERES JAMES E ,  GRUNER RONDALD H ,  MUNDIE CRAIG J ,  STEWART WILLIAM K ,  ZIEGLER MICHAEL L

IPC: G06F9/42 ,  G06F9/44 ,  G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/16 ,  G06F13/40 ,  G06F15/16 ,  G06F13/14 ,  G06F15/347

公开(公告)号：CA1302584C

公开(公告)日：1992-06-02

申请号：CA573400

申请日：1988-07-29

Applicant: ALLIANT COMPUTER SYSTEMS

Inventor： ZIEGLER MICHAEL L ,  FREDIEU ROBERT L ,  ACHILLES HEATHER D

IPC: G06F12/00 ,  G06F9/52 ,  G06F12/06 ,  G06F12/08 ,  G06F13/18 ,  G06F15/16 ,  G06F15/177

Abstract: A parallel processing computer is disclosed in which a plurality of memory elements (e.g., caches) are accessable by a plurality of processors, and in which a fixed access priority for the processors is varied periodically to reduce differences in processing times between the processors in applications where memory access conflicts occur. The variation in priority is done infrequently enough so as not to disturb the ability of the system to avoid memory access conflicts by falling into a "lockstep" condition, in which the fixed priority combined with a selected interleaving of the memory elements produces a memory access pattern that, for certain memory strides, produces no memory access conflicts.

公开(公告)号：CA1264493A1

公开(公告)日：1990-01-16

申请号：CA511838

申请日：1986-06-18

Applicant: ALLIANT COMPUTER SYSTEMS

Inventor： FREDIEU ROBERT L ,  GRUNER RONALD H ,  MCANDREW RICHARD T ,  MUNDIE CRAIG J ,  MYSZEWSKI MATHEW J ,  STEWART WILLIAM K ,  VERES JAMES E ,  ZIEGLER MICHAEL L

IPC: G06F9/42 ,  G06F9/44 ,  G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

Abstract: 412-1579 Disclosed is a digital computer for processing a program containing an iterative construct. The digital computer comprises a plurality of processors, each adapted for serially processing, without the assistance of the other said processors, those portions of the program outside of the iterative construct and each adapted for concurrently processing different iterations of the iterative construct. A mechanism is provided for activating those processors that have been idle at the start of the iterative construct and for transferring sufficient state information to the activated processors so that they can begin concurrent processing of iterations.

公开(公告)号：AU5893886A

公开(公告)日：1987-01-29

申请号：AU5893886

申请日：1986-06-20

Applicant: ALLIANT COMPUTER SYSTEMS

Inventor： BLAU JONATHAN SETH ,  FREDIEU ROBERT L ,  ZIEGLER MICHAEL L

IPC: G06F15/16 ,  G06F9/42 ,  G06F9/44 ,  G06F12/08 ,  G06F15/177 ,  G06F13/14

Abstract: A digital computer has a main memory, a cache connected to the main memory and a plurality of processors connected to the cache. Means permit each of the processors to access the same memory locations of the cache. The cache has means for concurrently accepting a current access from one of the processors while taking steps to complete a pending access made earlier by one of the processors.