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公开(公告)号：WO1991011726A1
公开(公告)日：1991-08-08
申请号：PCT/US1991000555
申请日：1991-01-25
Applicant: ALLIED-SIGNAL INC.
Inventor： ALLIED-SIGNAL INC. , ROBBINS, Daniel, C.
IPC: G01R23/10
Abstract: A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).
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