公开(公告)号：DE60129269T2

公开(公告)日：2008-04-17

申请号：DE60129269

申请日：2001-03-12

Applicant: ALTERA CORP A DELAWARE CORP

Inventor： NGAI TONY ,  PRASAD NITIN ,  TRAN THUNGOC

IPC: G11C8/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/00 ,  H03K19/177

Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

公开(公告)号：DE60129269D1

公开(公告)日：2007-08-23

申请号：DE60129269

申请日：2001-03-12

Applicant: ALTERA CORP A DELAWARE CORP

Inventor： NGAI TONY ,  PRASAD NITIN ,  TRAN THUNGOC

IPC: G11C8/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/00 ,  H03K19/177

Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.