公开(公告)号：WO1997019513A1

公开(公告)日：1997-05-29

申请号：PCT/US1996018302

申请日：1996-11-15

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KOVACS, Janos ,  KROESEN, Ronald ,  McCALL, Kevin

IPC: H03D03/24

CPC classification number: H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0996 ,  H03L7/14

Abstract: A dynamic phase selector phase locked loop circuit (20) includes: an A/D converter (24) for receiving an input signal (22) to be sampled; a phase detection circuit (26) for determining the phase error between the input signal (22) and a clock signal; a clock circuit (30), responsive to the phase detection circuit (26), for providing the clock signal to the A/D converter for timing the sampling of the input signal (22); the clock circuit (30) including a delay circuit having a number of delay taps; and a phase selector circuit (42), responsive to the phase detection circuit (26) for initially gating (43) the clock signals to the A/D converter from the clock circuit (30), and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Abstract translation: 动态相位选择器锁相环电路（20）包括：A / D转换器（24），用于接收待采样的输入信号（22）; 相位检测电路（26），用于确定输入信号（22）和时钟信号之间的相位误差; 响应于相位检测电路（26）的时钟电路（30），用于将时钟信号提供给A / D转换器，以对输入信号（22）的采样进行定时; 所述时钟电路（30）包括具有多个延迟抽头的延迟电路; 以及相位选择器电路（42），响应于所述相位检测电路（26），用于从时钟电路（30）首先将所述时钟信号选通（43）到所述A / D转换器，以及使所述延迟抽头之一动态地 调整时钟信号的相位并减少初始相位误差。