公开(公告)号：AU2003288480A1

公开(公告)日：2004-06-30

申请号：AU2003288480

申请日：2003-12-09

Applicant: ANALOG DEVICES INC

Inventor： GERAGHTY DONAL P ,  O'GRADY ALBERT C ,  WYNNE JOHN

IPC: H03M1/10 ,  H03M1/66

Abstract: A multi-channel circuit ( 1 ) comprising a plurality of on-chip channels (CH 1 to CH 4 ), each of which comprises a DAC ( 3 ) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit ( 11 ). The analogue output signals from the DACs ( 3 ) are outputted on output terminals ( 7 ) of the respective channels (CH 1 to CH 4 ). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs ( 3 ) are inputted to the interface and control logic circuit ( 11 ) through an I/O port ( 10 ). DAC registers ( 9 ) are provided in the respective channels (CH 1 to CH 4 ) for storing the digital words to be converted in the corresponding DACs ( 3 ). Analogue input terminals ( 20 ) are provided for receiving analogue input signals ( 20 ), for example, analogue signals from external systems which may be controlled by the output signals from the DACs ( 3 ). A multiplexer ( 15 ) is operable under the control of the interface and control logic circuit ( 11 ) for selectively and sequentially applying the analogue output signals from the DACs ( 3 ) and the analogue input signals from the analogue input terminals ( 20 ) to a monitoring output terminal ( 16 ) for facilitating independent monitoring of the analogue output signals from the DACs ( 3 ), and the analogue inputs on the analogue input terminals ( 20 ).

公开(公告)号：AU2003288481A1

公开(公告)日：2004-06-30

申请号：AU2003288481

申请日：2003-12-09

Applicant: ANALOG DEVICES INC

Inventor： GERAGHTY DONAL P ,  O'CONNOR DENIS MARTIN ,  DEMPSEY DENNIS ARNOLD

IPC: H03M1/10 ,  H03M1/66

公开(公告)号：WO2004068708A2

公开(公告)日：2004-08-12

申请号：PCT/IE2004000009

申请日：2004-01-23

Applicant: ANALOG DEVICES INC ,  GERAGHTY DONAL P ,  O'GRADY ALBERT C ,  VINEREANU TUDOR M

Inventor： GERAGHTY DONAL P ,  O'GRADY ALBERT C ,  VINEREANU TUDOR M

IPC: G06F1/025 ,  G06F1/03 ,  H03K4/02

CPC classification number: G06F1/025 ,  G06F1/0321 ,  H03K4/026

Abstract: A signal generator (1) for generating a square waveform analogue voltage output signal comprises an on-chip DAC (12) which outputs the analogue voltage signal on an output terminal (5). On-chip first and second programmable registers (9, 10) store first and second digital words which correspond to the maximum and minimum voltage values of the analogue output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9, 10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9, 10) to the DAC register (17). The frequency of the analogue output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.

Abstract translation: 用于产生方波模拟电压输出信号的信号发生器（1）包括在输出端（5）上输出模拟电压信号的片上DAC（12）。 片上第一和第二可编程寄存器（9,10）存储对应于模拟输出信号的最大和最小电压值的第一和第二数字字。 片上开关电路（15）选择性地并且交替地将第一和第二寄存器（9,10）切换到片上DAC寄存器（17），从而将相应的第一和第二数字字从该寄存器加载到DAC（12）中， 响应于由控制电路（14）产生的负载DAC信号。 响应于施加到LDAC端子（22）的时钟信号形式的外部产生的LDAC信号产生负载DAC信号。 响应于负载DAC信号的触发器（19）在控制线（25）上输出用于交替地将第一和第二寄存器（9,10）切换到DAC寄存器（17）的控制信号。 模拟输出信号的频率由LDAC信号的频率决定，为LDAC信号频率的一半。