CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER
    1.
    发明申请
    CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER 审中-公开
    充电重新分配数字到模拟转换器

    公开(公告)号:WO2012129289A3

    公开(公告)日:2014-04-24

    申请号:PCT/US2012029920

    申请日:2012-03-21

    Inventor: KAPUSTA RONALD

    CPC classification number: H03M1/0863 H03M1/804 H03M1/806

    Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

    Abstract translation: 本公开的实施例可以提供具有片上存储电容器的电荷再分配DAC,以代替传统的外部参考电压来向DAC提供电荷。 DAC可以包括具有第一板和第二板的片上储存电容器,用于产生DAC输出的DAC电容器阵列,以及由DAC输入字控制的开关阵列,以将DAC电容器耦合到储存器电容器 。 电荷再分配DAC还可以包括将第一板连接到用于第一外部参考电压的外部端子的第一开关和将第二板连接到外部端子用于第二外部参考电压的第二开关。 一个实施例可以提供包括电荷再分配DAC的ADC。

    SELF TIMED DIGITAL-TO-ANALOG CONVERTER
    2.
    发明公开
    SELF TIMED DIGITAL-TO-ANALOG CONVERTER 有权
    自同步的数字模拟转换器

    公开(公告)号:EP2697905A4

    公开(公告)日:2015-03-18

    申请号:EP12770799

    申请日:2012-04-11

    CPC classification number: H03M1/125 H03M1/462

    Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

    CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER
    3.
    发明公开
    CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER 有权
    数字模拟服务器MIT LADUNGSUMVERTEILUNG

    公开(公告)号:EP2689534A4

    公开(公告)日:2015-06-03

    申请号:EP12761428

    申请日:2012-03-21

    Inventor: KAPUSTA RONALD

    CPC classification number: H03M1/0863 H03M1/804 H03M1/806

    Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

    Abstract translation: 本公开的实施例可以提供具有片上存储电容器的电荷再分配DAC,以代替传统的外部参考电压来向DAC提供电荷。 DAC可以包括具有第一板和第二板的片上储存电容器,用于产生DAC输出的DAC电容器阵列,以及由DAC输入字控制的开关阵列,以将DAC电容器耦合到储存器电容器 。 电荷再分配DAC还可以包括将第一板连接到用于第一外部参考电压的外部端子的第一开关和将第二板连接到外部端子用于第二外部参考电压的第二开关。 一个实施例可以提供包括电荷再分配DAC的ADC。

    PRE-CHARGED CAPACITIVE DIGITAL-TO-ANALOG CONVERTER
    5.
    发明公开
    PRE-CHARGED CAPACITIVE DIGITAL-TO-ANALOG CONVERTER 审中-公开
    VORGELADENER KAPAZITIVER数字模拟服务器

    公开(公告)号:EP2702692A4

    公开(公告)日:2015-01-07

    申请号:EP12777805

    申请日:2012-04-26

    Inventor: KAPUSTA RONALD

    CPC classification number: H03M1/0845 H03M1/804

    Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.

    Abstract translation: 本公开的实施例可以提供具有两组电容器的电荷再分配DAC,其通过在多对电容器之间共享电荷来提供DAC输出,代替使用传统的外部参考电压对电容器充电。 电荷再分配DAC可以包括多对第一和第二电容器,每对电容器具有第一侧和第二侧,以及一组第一开关和一组第二开关。 每个第一或第二开关根据DAC输入字选择性地控制相应的第一或第二电容器的第一侧与一对输出信号线之一的连接。 电荷再分配DAC还可以包括一组桥接开关,每个桥接开关连接在成对的第一和第二电容器的第二侧之间。

    BALANCED IMPEDANCE METHOD FOR DIFFERENTIAL SIGNALING
    6.
    发明公开
    BALANCED IMPEDANCE METHOD FOR DIFFERENTIAL SIGNALING 有权
    IMPEDANZAUSGLEICHSVERFAHRENFÜREINE DIFFERENTIALSIGNALISIERUNG

    公开(公告)号:EP2715937A4

    公开(公告)日:2014-12-10

    申请号:EP12794005

    申请日:2012-05-25

    CPC classification number: H03H7/38 H04L25/0274 H04L25/0276

    Abstract: A system and method for implementing a differential signaling driver with a common-mode voltage not equal to one half the power supply voltage using voltage-mode techniques. Embodiments of the present invention maintain balanced impedance at the signal output. In an embodiment, a driver may have multiple operating modes for each potential supply voltage or common-mode voltage. In an embodiment, each potential mode may involve configuring the driver by activating or deactivating switches or resistors in the driver and each potential mode may have different resistor values.

    Abstract translation: 一种使用电压模式技术实现不等于电源电压的一半的共模电压的差分信号驱动器的系统和方法。 本发明的实施例在信号输出端保持平衡阻抗。 在一个实施例中,驱动器可以具有用于每个潜在电源电压或共模电压的多种操作模式。 在一个实施例中,每个电位模式可以涉及通过激活或去激活驱动器中的开关或电阻来配置驱动器,并且每个电位模式可以具有不同的电阻器值。

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