公开(公告)号：AT347751T

公开(公告)日：2006-12-15

申请号：AT02739834

申请日：2002-05-17

Applicant: ANALOG DEVICES INC

Inventor： KEAVENEY MICHAEL F ,  LYDEN COLIN

IPC: H03L7/183 ,  G06F7/68 ,  H03L7/197

Abstract: A fractional-N synthesizer and method of phase synchronising the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronisation pulse at integer multiples of periods of the input reference signal and gating the synchronisation pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

公开(公告)号：WO2005004331A2

公开(公告)日：2005-01-13

申请号：PCT/US2004020509

申请日：2004-06-25

Applicant: ANALOG DEVICES INC ,  KEAVENEY MICHAEL F ,  TUTHILL MICHAEL

Inventor： KEAVENEY MICHAEL F ,  TUTHILL MICHAEL

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101 ,  H03L

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A differential charge pump PLL synthesizer with adjustable tuning voltage range including a voltage controlled oscillator responsive to a tuning voltage to provide an output frequency. A phase detector circuit is responsive to a reference frequency and the sub­multiple of the output frequency for generating up and down pulses. A differential charge pump is responsive to the up and down pulses for generating positive and negative differential current pulses. A loop filter is responsive to the positive and negative differential current pulses for providing a differential voltage. A differential amplifier circuit is responsive to the differential voltage and a shift voltage applied at a voltage terminal for shifting the output voltage range of the differential amplifier circuit to provide a predetermined tuning voltage range.

Abstract translation: 具有可调谐电压范围的差分电荷泵PLL合成器，包括响应调谐电压的压控振荡器以提供输出频率。 相位检测器电路响应于参考频率和输出频率的多数以产生上升和下降脉冲。 差分电荷泵响应于上升和下降脉冲以产生正和负的差分电流脉冲。 环路滤波器响应正和负差分电流脉冲以提供差分电压。 差分放大器电路响应于差分电压和施加在电压端子处的偏移电压，用于移位差分放大器电路的输出电压范围以提供预定的调谐电压范围。

公开(公告)号：WO2005002055A3

公开(公告)日：2006-05-04

申请号：PCT/US2004020546

申请日：2004-06-25

Applicant: ANALOG DEVICES INC ,  WALSH PATRICK ,  KEAVENEY MICHAEL F

Inventor： WALSH PATRICK ,  KEAVENEY MICHAEL F

IPC: H03L20060101 ,  H03L7/00 ,  H03L7/197 ,  H03D3/24

CPC classification number: H03L7/1976

Abstract: A fractional-N synthesizer (100') with programmable output phase including a phase locked loop (12) having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider (20). A synchronization circuit (102) responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator (106) is responsive to an input fraction F/M, where F is the fractional value, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit (302') is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.

Abstract translation: 具有可编程输出相位的分数N合成器（100'）包括具有输出信号的锁相环（12），所述输出信号的频率是输入参考信号的分数倍，所述锁相环包括分频器（20）。 响应于输入参考信号用于产生输入参考信号的M个周期的整数倍的同步脉冲的同步电路（102）。 内插器（106）响应于输入分数F / M，其中F是分数值，以向分频器提供作为平均等于输入分数的分数值的输出。 相位调整电路（302'）响应于同步电路，用于相对于输入参考信号改变输出信号的相位。

公开(公告)号：WO2005004315A2

公开(公告)日：2005-01-13

申请号：PCT/US2004020507

申请日：2004-06-25

Applicant: ANALOG DEVICES INC ,  KEAVENEY MICHAEL F ,  HUNT WILLIAM

Inventor： KEAVENEY MICHAEL F ,  HUNT WILLIAM

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101 ,  H02M

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A chopped charge pump with, matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one of each pair to provide up current pulses and the other of each pair to provide down current pulses and switching on in a second phase the other of each pair to provide up current pulses and the one of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

Abstract translation: 一种斩波电荷泵，具有包括第一对电流源，第二对电流源的匹配上升和下降脉冲，以及用于在每对中的第一相中接通以提供上升电流脉冲的开关电路，并且另一个 每对以提供下降电流脉冲并且在第二相中接通每对中的另一相以提供电流脉冲，并且每对中的每一对以提供下降电流脉冲以抵消电流对的电流响应中的误差。

公开(公告)号：WO2005002069A3

公开(公告)日：2005-08-04

申请号：PCT/US2004020256

申请日：2004-06-24

Applicant: ANALOG DEVICES INC ,  KEAVENEY MICHAEL F

Inventor： KEAVENEY MICHAEL F

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A fast lock phase lock loop (PLL) with minimal phase disturbance when switching from wide bandwidth mode to narrow bandwidth mode including a phase frequency detector (52), a charge pump (102), a loop filter (66) and a voltage controlled oscillator (70), and a sequencer circuit (82) for, at a first time, initiating an increase in the charge pump current to increase the loop gain to widen the loop bandwidth and initiating a decrease in the resistance in the loop filter to increase the phase margin of the PLL in the wide bandwidth mode; at a second time, initiating a reduction in the charge pump current to reduce the loop gain and bandwidth, and; at a third time, initiating an increase in the resistance in the loop filter (66) to increase the phase margin. of the PLL in the narrow bandwidth mode.

Abstract translation: 一种快速锁定锁相环（PLL），在从宽带宽模式切换到窄带宽模式时具有最小的相位扰动，包括相位频率检测器（52），电荷泵（102），环路滤波器（66）和压控振荡器 （70）和定序器电路（82），用于在第一时间启动电荷泵电流的增加以增加环路增益以加宽环路带宽并且开始环路滤波器中的电阻的降低以增加 在宽带宽模式下PLL的相位裕度; 在第二时间，开始减少电荷泵电流以减小环路增益和带宽，以及; 在第三时间，开始增加环路滤波器（66）中的电阻以增加相位裕量。 的PLL在窄带宽模式下。

公开(公告)号：WO2005001284A3

公开(公告)日：2005-07-21

申请号：PCT/US2004020136

申请日：2004-06-24

Applicant: ANALOG DEVICES INC ,  KEAVENEY MICHAEL F

Inventor： KEAVENEY MICHAEL F

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A pulse width modulated common mode feedback technique for a differential charge pump (16) includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up (30) and pump down pulses (32) to set up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.

Abstract translation: 用于差分电荷泵（16）的脉宽调制共模反馈技术包括对差分电荷泵的输出进行平均以确定共模电压; 从泵浦（30）和泵浦脉冲（32）产生以产生源脉冲和下降源脉冲以及一组上吸收脉冲和下降脉冲，并且响应于参考电压和公共电压之间的差异 模式电压，源和阱脉冲组中的至少一个的宽度以匹配参考共模电压。

公开(公告)号：WO2005004332A3

公开(公告)日：2005-05-26

申请号：PCT/US2004020550

申请日：2004-06-25

Applicant: ANALOG DEVICES INC ,  KEAVENEY MICHAEL F ,  LYDEN COLIN ,  WALSH PATRICK

Inventor： KEAVENEY MICHAEL F ,  LYDEN COLIN ,  WALSH PATRICK

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract translation: 用于快速锁定锁相环的电荷泵系统包括一组电荷泵单元; 以及控制逻辑电路，用于使该组n个电荷泵单元在宽带宽模式下产生具有标称电荷泵失配的上和下充电脉冲; 并且在窄带宽模式下，使得n个电荷泵单元的至少一个子集顺序地产生与宽带宽模式下的标称电荷泵失配相匹配的窄带宽模式下的平均电荷泵失配。

公开(公告)号：WO2005004333A2

公开(公告)日：2005-01-13

申请号：PCT/US2004020551

申请日：2004-06-25

Applicant: ANALOG DEVICES INC ,  LYDEN COLIN ,  KEAVENEY MICHAEL F ,  WALSH PATRICK

Inventor： LYDEN COLIN ,  KEAVENEY MICHAEL F ,  WALSH PATRICK

IPC: F04B20060101 ,  H02M20060101 ,  H03D13/00 ,  H03K3/017 ,  H03K3/0231 ,  H03L20060101 ,  H03L7/00 ,  H03L7/06 ,  H04B20060101 ,  H03L

CPC classification number: H03K3/0231 ,  H03L7/0896

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract translation: 用于分数N相位锁相环的增益补偿技术包括：将N分频器反馈信号的参考信号锁定在包括相位检测器，电荷泵，环路滤波器和压控振荡器的锁相环中，在其反馈环路中使用N分频器 ; 用包括至少一个积分器的Σ-Δ调制器驱动N分频器以获得预定的分数N反馈信号; 并且通过预定因子来指令锁相环增益的缩放，并且通过所述因子对至少一个积分器的内容进行同步反比。

公开(公告)号：EP1391043A4

公开(公告)日：2004-09-29

申请号：EP02739834

申请日：2002-05-17

Applicant: ANALOG DEVICES INC

Inventor： KEAVENEY MICHAEL F ,  LYDEN COLIN

IPC: H03L7/183 ,  G06F7/68 ,  H03L7/197

CPC classification number: H03L7/1976 ,  G06F7/68

Abstract: A fractional-N synthesiser (10) and method of phase synchronising the output signal with the input reference signal in a fractional-N synthesiser by generating a synchronisation pulse at integer multiples of periods of he input reference signal (28) and gating (44) the synchronisation pulse to re-initialise the interpolator (26) in the fractional-N synthesiser to synchronise the phase of the output signal with the input reference signal.

Abstract translation: 通过在输入参考信号（28）和选通（44）的整数倍周期处产生同步脉冲，在分数N合成器中使输出信号与输入参考信号相位同步的分数N合成器（10） 同步脉冲重新初始化分数N合成器中的内插器（26），以使输出信号的相位与输入参考信号同步。