公开(公告)号：JPH104352A

公开(公告)日：1998-01-06

申请号：JP2362297

申请日：1997-02-06

Applicant: ANALOG DEVICES INC

Inventor： CHRISTOPHER W MANGELSDORFF ,  NAKAMURA KATSUSHI

IPC: G11C27/02 ,  H03G11/00 ,  H03K5/08 ,  H03M1/10 ,  H03M1/18 ,  H04N5/18 ,  H04N5/20 ,  H04N5/357 ,  H04N5/361 ,  H04N5/372 ,  H04N5/378 ,  H04N5/335

Abstract: PROBLEM TO BE SOLVED: To clamp an input voltage level to a desired voltage within an operating range of the device by calibrating an offset level added to a signal and collating the signal with a desired reference level at an output. SOLUTION: A correlation double sampling circuit 71 samples two signals on an input line 24, low frequency noise and offset in common to both the samples are eliminated and a difference signal is outputted. A black level correction circuit 77' calibrates the offset level so as to obtain a desired reference level at the output of the device. Then a clamp circuit, controls an output voltage of the correlation double sampling circuit 71 and a desired voltage level at an input of the correlation double sampling circuit 71 so as to servo within a device supply range and the operating range.

公开(公告)号：JP2013110769A

公开(公告)日：2013-06-06

申请号：JP2013047772

申请日：2013-03-11

Applicant: Analog Devices Inc ,  アナログ デバイセス インコーポレーテッドAnalog Devices,Incorporated

Inventor： NAKAMURA KATSUSHI

IPC: H03G3/12 ,  H03M1/18 ,  H03F3/34 ,  H03G1/04 ,  H03G3/02 ,  H03G3/10 ,  H04N5/16 ,  H04N5/20 ,  H04N5/357 ,  H04N5/372 ,  H04N5/378

CPC classification number: H04N5/20 ,  H04N5/16 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/372 ,  H04N5/378

Abstract: PROBLEM TO BE SOLVED: To provide a CCD signal processing channel with input and output offset correction.SOLUTION: A variable gain amplifier circuit includes: a correlated double sampling circuit 1202 for removing an unwanted correlated noise component from an input signal; a first programmable gain amplifier 104 positioned downstream of the correlated double sampling circuit; a first offset correction circuit 500 having an input connected to an input of the first programmable gain amplifier and an output connected to an input of the correlated double sampling circuit to provide a first offset correction for at least either of an offset of the input signal and an offset of the correlated double sampling circuit; an analog/digital converter 106 positioned downstream of the first programmable gain amplifier; a second offset correction circuit 502 positioned downstream of the first programmable gain amplifier to provide a second offset correction; and a pixel gain amplifier 1204 positioned downstream of the correlated double sampling circuit and upstream of the first programmable gain amplifier.

Abstract translation: 要解决的问题：提供具有输入和输出偏移校正的CCD信号处理通道。 解决方案：可变增益放大器电路包括：相关双采样电路1202，用于从输入信号中去除不需要的相关噪声分量; 位于相关双采样电路下游的第一可编程增益放大器104; 第一偏移校正电路500，其具有连接到第一可编程增益放大器的输入端的输入端和连接到相关双采样电路的输入端的输出端，以提供输入信号的偏移中的至少一个的第一偏移校正;以及 相关双采样电路的偏移; 位于第一可编程增益放大器下游的模拟/数字转换器106; 位于第一可编程增益放大器下游的第二偏移校正电路502提供第二偏移校正; 以及位于相关双采样电路的下游和第一可编程增益放大器的上游的像素增益放大器1204。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011130501A

公开(公告)日：2011-06-30

申请号：JP2011039227

申请日：2011-02-25

Applicant: Analog Devices Inc ,  アナログ デバイセス インコーポレーテッドAnalog Devices,Incorporated

Inventor： NAKAMURA KATSUSHI

IPC: H03G1/04 ,  H03M1/18 ,  H03F3/34 ,  H03G3/10 ,  H04N5/16 ,  H04N5/20 ,  H04N5/357 ,  H04N5/372 ,  H04N5/378

CPC classification number: H04N5/20 ,  H04N5/16 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/372 ,  H04N5/378

Abstract: PROBLEM TO BE SOLVED: To provide a CCD signal processing channel with an input and an output offset correction function.
SOLUTION: Integrators are positioned to provide correction at the input of a correlated double sampling circuit and at the output of a programmable gain amplifier. A gain control function is provided for the programmable gain amplifier. The second integrator may be all digital or may combine analog and digital signals. The channel may also be constructed using a digital programmable gain amplifier. The digital programmable gain amplifier can be combined with an analog programmable gain amplifier in the signal processing channel.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供具有输入和输出偏移校正功能的CCD信号处理通道。 解决方案：积分器被定位成在相关双采样电路的输入端和可编程增益放大器的输出处提供校正。 为可编程增益放大器提供增益控制功能。 第二个积分器可以是全数字的，或者可以组合模拟和数字信号。 信道也可以使用数字可编程增益放大器来构造。 数字可编程增益放大器可以与信号处理通道中的模拟可编程增益放大器组合。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2001036358A

公开(公告)日：2001-02-09

申请号：JP2000179750

申请日：2000-06-15

Applicant: ANALOG DEVICES INC

Inventor： NAKAMURA KATSUSHI

IPC: H03M1/18 ,  H03F3/34 ,  H03G1/04 ,  H03G3/10 ,  H04N5/16 ,  H04N5/20 ,  H04N5/357 ,  H04N5/372 ,  H04N5/378

Abstract: PROBLEM TO BE SOLVED: To eliminate offsets of a charge coupled device(CCD) and a correlation double sampling circuit(CDS) at a simplified circuit and by a low power consumption by equipping a first offset correction circuit on an upstream side of a programmable gain amplifier and a second offset correction circuit on a downstream side of the programmable gain amplifier. SOLUTION: In this system, two offset correction loops are applied. That is, one is applied to an input 500 of a PGA 104 and the other to an output 502 of the PGA 104. With the correction of an input offset, an offset of a CCD and the offset of a CDS 102 are eliminated. Output offset correction next eliminates an input offset of the PGA 104 and uncorrected offset from a first offset correction which is called an output of the PGA 104. Since almost all offset contributions are eliminated before the PGA 104, offsets which an output loop has to correct are reduced greatly.

公开(公告)号：JP2001028716A

公开(公告)日：2001-01-30

申请号：JP2000175026

申请日：2000-06-12

Applicant: ANALOG DEVICES INC

Inventor： NAKAMURA KATSUSHI ,  STEVE DEKKER

IPC: G11C27/02 ,  H03F3/70 ,  H03G3/10 ,  H03G3/30 ,  H04N5/335 ,  H04N5/357 ,  H04N5/363 ,  H04N5/372 ,  H04N5/378

Abstract: PROBLEM TO BE SOLVED: To provide a correlated double sampling(CDS) circuit, a pixel signal gain amplifier circuit (PxGA) circuit and a CDS/PxGA circuit where a gain setting value of an amplifier circuit can be changed for each sampling. SOLUTION: The CDS/PxGA circuit is provided with a main amplifier 800, an input sampling capacitor 802 and a feedback capacitor 804. The input sampling capacitor 802 samples an input signal for a 1st period, and the feedback capacitor 804 samples the sampled input as above for a 2nd period. No sampling switch is provided between the input sampling capacitor 802 and an input terminal of the main amplifier 800. The feedback capacitor 804 may be made up of a capacitor array.