Simultaneous data transfer and error control to reduce latency and improve throughput to a host

    公开(公告)号:AU2012302094A1

    公开(公告)日:2014-01-16

    申请号:AU2012302094

    申请日:2012-08-28

    Applicant: APPLE INC

    Abstract: The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.

    METHODS AND APPARATUS FOR DYNAMIC THERMAL CONTROL

    公开(公告)号:HK1125203A1

    公开(公告)日:2009-07-31

    申请号:HK09103253

    申请日:2009-04-07

    Applicant: APPLE INC

    Abstract: Methods and apparatuses for dynamically budgeting power usage to control temperatures in a data processing system. In one aspect, a data processing system includes: a first sensor to determine an ambient temperature of an environment in which the data processing system is; and a controller (e.g., a microcontroller or a microprocessor) coupled to the sensor to control operations of the data processing system according to the ambient temperature. In one example, the data processing system further includes a second sensor to determine an actual temperature of a component of the data processing system. In one example, a controller is coupled to the temperature sensors to determine an operating setting of the data processing system based on a prediction of a temperature of the data processing system which is a function of the plurality of actual temperatures and the operating setting of the data processing system.

    Simultaneous data transfer and error control to reduce latency and improve throughput to a host

    公开(公告)号:AU2012302094B2

    公开(公告)日:2016-02-18

    申请号:AU2012302094

    申请日:2012-08-28

    Applicant: APPLE INC

    Abstract: The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.

    TRANSFERENCIA DE DATOS SIMULTANEA Y CONTROL DE ERROR PARA REDUCIR LA LATENCIA Y MEJORAR LA CAPACIDAD DE PROCESAMIENTO A UN ANFITRION.

    公开(公告)号:MX2013015121A

    公开(公告)日:2014-03-31

    申请号:MX2013015121

    申请日:2012-08-28

    Applicant: APPLE INC

    Abstract: Las modalidades descritas proporcionan un sistema que transfiere datos desde un dispositivo de almacenamiento a un anfitrión. El sistema incluye un mecanismo de comunicación que recibe una solicitud para leer un conjunto de bloques desde el anfitrión. Después, tras leer cada bloque del conjunto de bloques desde el dispositivo de almacenamiento, el mecanismo de comunicación transfiere el bloque a través de una interfaz con el anfitrión. El sistema también incluye un aparato de detección de error que realiza la detección de error en el bloque tras leer el bloque y un aparato de corrección de error que realiza corrección de error en el bloque si se detecta un error en el bloque. El mecanismo de comunicación puede entonces retransferir el bloque al anfitrión después de que el error es eliminado del bloque.

    FORCED IDLE OF A DATA PROCESSING SYSTEM
    5.
    发明申请
    FORCED IDLE OF A DATA PROCESSING SYSTEM 审中-公开
    数据处理系统的强制空闲

    公开(公告)号:WO2009088451A2

    公开(公告)日:2009-07-16

    申请号:PCT/US2008014036

    申请日:2008-12-23

    Abstract: Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. One or more constraint parameters of a system are monitored. The data processing system is forced into an idle state for a first portion of a time while allowed to operate for a second portion of the time based on the one or more constraint parameters, wherein the system is forced into the idle state in response to comparing a target idle time to an actual idle time. The target idle time of the system is determined, in one embodiment, based on the one or more constraint parameters. The actual idle time of the system may be monitored to take into account interrupts which disrupt an idle time and idle times resulting from no software instructions to execute. The system may be allowed to operate based on comparisons of the target idle time and the actual idle time.

    Abstract translation: 描述了用于管理数据处理系统的功率的方法和装置的示例性实施例。 监视系统的一个或多个约束参数。 数据处理系统在一段时间内被强制进入空闲状态,同时基于一个或多个约束参数允许对时间的第二部分进行操作,其中响应于比较而将系统强制进入空闲状态 目标空闲时间到实际空闲时间。 在一个实施例中,基于一个或多个约束参数确定系统的目标空闲时间。 可以监视系统的实际空闲时间以考虑中断,其中断由空闲时间和空闲时间所导致的无软件指令执行。 可以基于目标空闲时间和实际空闲时间的比较来允许系统操作。

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