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公开(公告)号：JP2007193811A
公开(公告)日：2007-08-02
申请号：JP2007009576
申请日：2007-01-18
Applicant: Apple Inc , アップル インコーポレイテッド
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
CPC classification number: G11C29/883 , G11C16/04 , G11C29/83 , G11C29/88 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide articles and associated methods and systems for disabling defective flash memory dies in a device containing multiple flash memory dies. SOLUTION: Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供用于在包含多个闪速存储器管芯的设备中禁用有缺陷的闪存存储器管芯的物品和相关方法和系统。
解决方案：包含多个闪存芯片的软件包可能会被标记为基于未禁用的闪存芯片来指示闪存数据存储容量。 可以在管芯级，封装级和/或板级应用各种禁用方法。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2011108267A
公开(公告)日：2011-06-02
申请号：JP2011020057
申请日：2011-02-01
Applicant: Apple Inc , アップル インコーポレイテッド
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
IPC: G06F12/16
CPC classification number: G11C29/883 , G11C16/04 , G11C29/83 , G11C29/88 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide articles and associated methods and systems for disabling defective flash memory dies in a device containing a plurality of flash memory dies. SOLUTION: Packages containing a plurality of flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供用于在包含多个闪速存储器管芯的装置中禁用有缺陷的闪速存储器管芯的物品和相关方法和系统。 解决方案：包含多个闪速存储器管芯的软件包可以被标记为基于不被禁用的闪速存储器管芯来指示闪速存储器数据存储容量。 可以在管芯级，封装级和/或板级应用各种禁用方法。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2007193810A
公开(公告)日：2007-08-02
申请号：JP2007009575
申请日：2007-01-18
Applicant: Apple Inc , アップル インコーポレイテッド
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
CPC classification number: G06F12/0607 , G06F2212/1028 , G06F2212/2022 , Y02D10/13
Abstract: PROBLEM TO BE SOLVED: To provide articles, and associated methods and systems related to selecting read interleaving policies independently of selecting write interleaving policies. SOLUTION: In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operation mode. Examples of operating modes may include (1) reading or writing to a flash memory when connected to an external power source, (2) reading from the flash memory when powered by a portable power source (e.g., battery), and (3) writing to the flash memory when powered by a portable power supply. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提供与选择写入交错策略无关的选择读取交错策略的文章以及相关的方法和系统。 解决方案：在各种实现中，选择在操作期间可以是静态的或动态的。 在动态地选择读交错策略和写入交错策略的实现中，该选择可以基于各种操作条件，例如温度，电源，电池电压和操作模式。 操作模式的示例可以包括：（1）当连接到外部电源时读取或写入闪速存储器，（2）当由便携式电源（例如，电池）供电时，从闪存读取，以及（3）写入 通过便携式电源供电到闪存。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2012185850A
公开(公告)日：2012-09-27
申请号：JP2012122367
申请日：2012-05-29
Applicant: Apple Inc , アップル インコーポレイテッド
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
IPC: G06F12/16 , H01L21/336 , H01L21/8247 , H01L23/00 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC classification number: G11C29/883 , G11C16/04 , G11C29/83 , G11C29/88 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a product and associated method and system for disabling defective flash memory dies in a device containing a plurality of flash memory dies.SOLUTION: A label, to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled, may be attached to packages containing a plurality of flash memory dies. Various disabling methods may be applied at a die level, a package level, and/or a board level.
Abstract translation: 要解决的问题：提供一种产品及其相关方法和系统，用于在包含多个闪速存储器管芯的装置中禁用有缺陷的闪速存储器管芯。 解决方案：用于指示基于未被禁用的闪存存储器的闪速存储器数据存储容量的标签可以被附加到包含多个闪速存储器管芯的封装。 可以在管芯级，封装级和/或板级应用各种禁用方法。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JP2012043451A
公开(公告)日：2012-03-01
申请号：JP2011218262
申请日：2011-09-30
Applicant: Apple Inc , アップル インコーポレイテッド
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
IPC: G06F12/06
CPC classification number: G06F12/0607 , G06F2212/1028 , G06F2212/2022 , Y02D10/13
Abstract: PROBLEM TO BE SOLVED: To provide articles and associated methods and systems related to selecting read interleaving policies independently of selecting write interleaving policies.SOLUTION: Systems for data processing using interleaved memory include: a power source; multiple memory elements operational by connection to the power source; a memory controller which selectively controls an interleave ratio of access to the multiple memory elements; and a processor which receives an instruction. The instruction makes the processor make the memory controller run a process to specify the interleave ratio. The process receives an access request to the memory element. A peak current extracted to the memory from the power source to process the received access request is controlled by selecting the interleave ratio to run the access request.
Abstract translation: 要解决的问题：提供与选择读交错策略相关的文章和相关方法和系统，与选择写交错策略无关。 解决方案：使用交错存储器的数据处理系统包括：电源; 通过连接到电源可操作的多个存储元件; 存储器控制器，其选择性地控制对所述多个存储器元件的访问的交织比; 以及接收指令的处理器。 指令使处理器使存储器控制器运行一个过程来指定交错比。 该进程接收对存储器元件的访问请求。 通过选择交织比来控制从电源提取到存储器以处理接收的访问请求的峰值电流以运行访问请求。 版权所有（C）2012，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：AT480856T
公开(公告)日：2010-09-15
申请号：AT07000800
申请日：2007-01-16
Applicant: APPLE INC
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
Abstract: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.
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公开(公告)号：DE602007008963D1
公开(公告)日：2010-10-21
申请号：DE602007008963
申请日：2007-01-16
Applicant: APPLE INC
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
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公开(公告)号：HK1159307A1
公开(公告)日：2012-07-27
申请号：HK11113285
申请日：2011-12-08
Applicant: APPLE INC
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
IPC: G11C20060101
Abstract: Systems and methods, including computer software, for reading data from a flash memory cell (124) involve detecting voltages from a group of memory cells. The group of memory cells have associated metadata for error detection (605), and each memory cell stores a voltage representing a data value selected from a plurality of possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages (610). Alternative data values for the memory cells having the uncertain data values are determined (615). A combination of alternative data values is selected (625), and an error detection test is performed (635) using the metadata associated with the memory cells and the selected combination of alternative data values.
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公开(公告)号：DE602007007938D1
公开(公告)日：2010-09-02
申请号：DE602007007938
申请日：2007-05-14
Applicant: APPLE INC
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
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公开(公告)号：AT475183T
公开(公告)日：2010-08-15
申请号：AT07762158
申请日：2007-05-14
Applicant: APPLE INC
Inventor： CORNWELL MICHAEL J , DUDTE CHRISTOPHER P
Abstract: Systems and methods, including computer software, for reading data from a flash memory cell (124) involve detecting voltages from a group of memory cells. The group of memory cells have associated metadata for error detection (605), and each memory cell stores a voltage representing a data value selected from a plurality of possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages (610). Alternative data values for the memory cells having the uncertain data values are determined (615). A combination of alternative data values is selected (625), and an error detection test is performed (635) using the metadata associated with the memory cells and the selected combination of alternative data values.
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