Abstract:
Methods and apparatuses are disclosed to estimate temperature at one or more critical points in a data processing system comprising modeling a steady state temperature portion of a thermal model at the one or more critical points using regression analysis; modeling the transient temperature portion of the thermal model at the one or more critical points using a filtering algorithm; and generating a thermal model at the one or more critical points by combining the steady state temperature portion of the thermal model with the transient temperature portion of the thermal model. The thermal model may then be used to estimate an instantaneous temperature at the one or more critical points or to predict a future temperature at the one or more critical points.
Abstract:
The disclosed embodiments provide an apparatus that controls a cooling system for a computer system. During operation, the apparatus monitors a temperature signal from the computer system to determine a trend for the temperature signal. Then, a filter parameter for a trend-based filter is selected based on the trend. Next, the temperature signal is filtered using the trend-based filter to generate a filtered temperature signal which is then passed through a controller to generate a control signal for the cooling system.
Abstract:
A linked multiple independent control system can include two or more independent controllers configured to cooperatively control operating points of a system. In one particular embodiment, the linked multiple independent control system can control operating temperatures of a computing device. In one embodiment, the independent controllers can operate in parallel to develop control effort signals that are used by the computing device to affect operating parameters of one or more components included in the computing device. In another embodiment, independent controllers can have independent temperature thresholds that can affect control effort signals only from the related controller.
Abstract:
A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.
Abstract:
A thermal manager has a digital filter whose input is to receive raw temperature values from a sensor and whose output is to provide processed or filtered temperature values according to a filter function that correlates temperature at the sensor with temperature at another location in the device. The thermal manager has a look-up table that further correlates temperature at the sensor with temperature at said another location. The look-up table contains a list of processed temperature sensor values, and/or a list of temperatures representing the temperature at said another location, and their respective power consumption change commands. The thermal manager accesses the look-up table using selected, filtered temperature values, to identify their respective power consumption change commands. The latter are then evaluated and may be applied, to mitigate a thermal at said another location. Other embodiments are also described and claimed.
Abstract:
In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
Abstract:
In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
Abstract:
Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. One or more constraint parameters of a system are monitored. The data processing system is forced into an idle state for a first portion of a time while allowed to operate for a second portion of the time based on the one or more constraint parameters, wherein the system is forced into the idle state in response to comparing a target idle time to an actual idle time. The target idle time of the system is determined, in one embodiment, based on the one or more constraint parameters. The actual idle time of the system may be monitored to take into account interrupts which disrupt an idle time and idle times resulting from no software instructions to execute. The system may be allowed to operate based on comparisons of the target idle time and the actual idle time.
Abstract:
A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.
Abstract:
Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. A constraint parameter of a system operating at a first frequency and a first voltage is monitored. The system is, based on the monitoring of the constraint parameter, forced into an idle state while operating at a second frequency and a second voltage. The idle state prevents instructions from being executed.