SYSTEMS AND METHODS FOR CALIBRATING A DISPLAY TO REDUCE OR ELIMINATE MURA ARTIFACTS
    1.
    发明申请
    SYSTEMS AND METHODS FOR CALIBRATING A DISPLAY TO REDUCE OR ELIMINATE MURA ARTIFACTS 审中-公开
    用于校准显示器以减少或消除木瓜作物的系统和方法

    公开(公告)号:WO2014004476A1

    公开(公告)日:2014-01-03

    申请号:PCT/US2013/047573

    申请日:2013-06-25

    Applicant: APPLE INC.

    Abstract: Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays 18. For example, pixels 102 may be programmed to a uniform gray level before all or a substantial number of gates 116 of the pixels 102 are activated. The voltages on some or all source lines 106 that supply the pixels 102 may be measured. A mura artifact may be seen when voltage differences on the source lines 106 are present. As such, operational parameters of the electronic display 18 may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

    Abstract translation: 提供了系统,方法和设备以减少或消除电子显示器18上的mura伪像。例如,像素102的所有或相当数量的门116被激活之前,可将像素102编程为均匀的灰度级。 可以测量供应像素102的一些或所有源极线106上的电压。 当存在源极线106上的电压差时,可以看到一个阴影伪像。 因此,可以调整电子显示器18的操作参数,以通过减小电压差来减少或消除凹陷伪像。

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