公开(公告)号：WO2015013080A1

公开(公告)日：2015-01-29

申请号：PCT/US2014/046865

申请日：2014-07-16

Applicant: APPLE INC.

Inventor： RAGHUVANSHI, Pankaj ,  KUMAR, Rohit ,  PERIYACHERI, Suresh

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value.

Abstract translation: 公开了一种用于对计算系统执行指令调节的装置。 该装置可以包括第一计数器，第二计数器和控制电路。 第二计数器可以被配置为响应于处理器的处理周期的确定已经完成而递增。 控制电路可以被配置为初始化第一和第二计数器，检测处理器已经发出和指令，响应于所发出的指令的检测而减小第一计数器，阻止处理器发出指令，取决于第一和第二计数器的值 计数器，根据第二计数器的值复位第一计数器，并且响应于第二计数器的值大于预定值的确定而复位第二计数器。