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    SMART EXTERNAL INTERFERENCE DETECTION AND AVOIDANCE FOR WIRELESS COMMUNICATION
    1.
    发明公开
    SMART EXTERNAL INTERFERENCE DETECTION AND AVOIDANCE FOR WIRELESS COMMUNICATION 审中-公开

    公开(公告)号：US20240098655A1

    公开(公告)日：2024-03-21

    申请号：US17947964

    申请日：2022-09-19

    Applicant: Apple Inc.

    Inventor： Sathish Shanbhag Kota ,  Vijay Kumar Ramamurthi ,  Vijaykrishnan Ramakrishnan

    IPC: H04W52/36 ,  H04W52/02

    CPC classification number: H04W52/367 ,  H04W52/0245

    Abstract: Techniques described herein are directed toward smart external interference detection and avoidance. An example method includes determining a first received signal strength indicator (RSSI) value of a received first signal across a radio band, wherein the first RSSI value is based at least in part on a second signal transmitted by an interfering device. The first received RSSI value is compared with a threshold value. A first gain adjustment value is determined for a receiver chain of the first computing device and a second gain adjustment value of a transmitter chain based at least in part on the comparison. A first gain of a first amplifier of the receiver chain is adjusted based at least in part on the first gain adjustment value. A second gain of a second amplifier of the transmitter chain is adjusted based at least in part on the second gain adjustment value.

    SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS
    2.
    发明公开
    SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS 审中-公开

    公开(公告)号：US20230222076A1

    公开(公告)日：2023-07-13

    申请号：US18124332

    申请日：2023-03-21

    Applicant: Apple Inc.

    Inventor： Helena Deirdre O’Shea ,  Camille Chen ,  Vijay Kumar Ramamurthi ,  Alon Paycher ,  Matthias Sauer ,  Bernd W. Adler

    IPC: G06F13/40

    CPC classification number: G06F13/4068 ,  G06F2213/40

    Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

    System for link management between multiple communication chips
    5.
    发明授权
    System for link management between multiple communication chips 有权

    公开(公告)号：US11640365B2

    公开(公告)日：2023-05-02

    申请号：US17500325

    申请日：2021-10-13

    Applicant: Apple Inc.

    Inventor： Helena Deirdre O'Shea ,  Camille Chen ,  Vijay Kumar Ramamurthi ,  Alon Paycher ,  Matthias Sauer ,  Bernd W. Adler

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/24 ,  G06F11/34 ,  G06F11/30 ,  G06F13/28

    Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

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