公开(公告)号：AU3309799A

公开(公告)日：1999-09-15

申请号：AU3309799

申请日：1999-02-24

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/46 ,  H05K7/14

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. A set of common points is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. The inductance of longer traces is reduced by merging traces near a central portion of the backplane to form a conductive region that extends to at least one connector on either side of the common points, thereby electrically shortening the longer traces. The inductance is further reduced by widening the longer traces. Longer traces are wider than shorter traces to reduce the differences in the LC products associated with each trace and, therefore, the differences in delay among the traces.

公开(公告)号：AU2458897A

公开(公告)日：1997-11-07

申请号：AU2458897

申请日：1997-04-11

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14

公开(公告)号：CA2322151A1

公开(公告)日：1999-09-02

申请号：CA2322151

申请日：1999-02-24

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/46 ,  H05K7/14

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. A set of common points (23) is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. The inductance of longer traces is reduced by merging traces near a central portion of the backplane to form a conductive region (23) that extends to at least one connector (34, 31) on either side of the common points, thereby electrically shortening the longer traces. The inductance is further reduced by widening the longer traces. Longer traces are wider than shorter traces to reduce the differences in the LC products associated with each trace and, therefore, the differences in delay among the traces.

公开(公告)号：WO9944400A3

公开(公告)日：1999-12-02

申请号：PCT/US9903953

申请日：1999-02-24

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/46 ,  H05K7/14

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09727

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. A set of common points (23) is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. The inductance of longer traces is reduced by merging traces near a central portion of the backplane to form a conductive region (23) that extends to at least one connector (34, 31) on either side of the common points, thereby electrically shortening the longer traces. The inductance is further reduced by widening the longer traces. Longer traces are wider than shorter traces to reduce the differences in the LC products associated with each trace and, therefore, the differences in delay among the traces.

Abstract translation: 数据处理系统包括通过多个连接器连接到背板的背板和多个逻辑板。 一组公共点（23）通过每个公共点和连接器的相应引脚之间的各个导电迹线电耦合到连接器。 通过在背板的中心部分附近合并迹线来形成较长迹线的电感，以形成延伸到公共点两侧的至少一个连接器（34,31）的导电区域（23），从而电气缩短 痕迹。 通过加宽更长的走线来进一步减小电感。 较长的迹线比较短的迹线更宽，以减少与每个迹线相关联的LC产物的差异，并因此减少迹线之间的延迟差异。

公开(公告)号：EP0958717A4

公开(公告)日：2002-07-24

申请号：EP97920374

申请日：1997-04-11

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09263

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. In one embodiment of the invention, a set of common points (23, 24) is electrically coupled to the connectors by individual conductive traces between each common point (23) and the corresponding pins (31-36) of the connectors. The common points are preferably centrally located among the plurality of connectors to reduce propagation delay. A connector (75) can be attached at the common points. The traces are separated from each other by lateral displacement in a single plane. If the backplane is a multi-layered printed circuit board, the traces are separated from each other by vertical displacement between the layers of the printed circuit board or by both vertical and horizontal displacement. The traces to the connectors nearest the common points (83) have a minimum length (96) greater than the distance (92) between the nearest connectors and the common points.