公开(公告)号：WO2017184357A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/026518

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW ,  ASM AMERICA, INC.

Inventor： KNAEPEN, Werner ,  MAES, Jan, Willem ,  STOKHOF, Maarten ,  GRONHEID, Roel ,  SRIRAMAN, Hari, Pathangi

IPC: H01L21/027 ,  H01L21/768

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10 - 2000 Pa.

Abstract translation: 通过以下步骤在衬底上形成定向自组装（DSA）层的方法：提供衬底; 在衬底上施加包含自组装材料的层; 以及通过在衬底周围提供受控的温度和气体环境来退火该层的自组装材料以形成定向的自组装层。 受控的气体环境包含分子，该分子包含分压在10-2000Pa之间的氧元素

公开(公告)号：WO2006091510A1

公开(公告)日：2006-08-31

申请号：PCT/US2006/005868

申请日：2006-02-21

Applicant: ASM AMERICA, INC. ,  KUMAR, Davendra ,  GOUNDAR, Kamal, Kishore ,  KEMELING, Nathanael, R.C. ,  FUKUDA, Hideaki ,  SPREY, Hessel ,  STOKHOF, Maarten

Inventor： KUMAR, Davendra ,  GOUNDAR, Kamal, Kishore ,  KEMELING, Nathanael, R.C. ,  FUKUDA, Hideaki ,  SPREY, Hessel ,  STOKHOF, Maarten

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/02063 ,  C23C14/02 ,  C23C16/02 ,  C23C16/36 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed (100) in insulating layers. The layers are then adequately treated with a particular plasma process (101). Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction (115) can occur without significantly filling the pores forming improved interconnects.

Abstract translation: 提供了集成电路中双镶嵌结构的保形衬里的方法和结构。 优选实施例涉及在多孔材料中形成的开口上提供适形衬里。 在绝缘层中形成沟槽（100）。 然后用特定的等离子体处理（101）充分处理各层。 在这种等离子体处理之后，可以发生自限制的自饱和原子层沉积（ALD）反应（115）而不显着填充形成改进的互连的孔。

公开(公告)号：EP1851794A1

公开(公告)日：2007-11-07

申请号：EP06735499.3

申请日：2006-02-21

Applicant: ASM America, Inc.

Inventor： SPREY, Hessel ,  FUKUDA, Hideaki, Tsuduki-ku ,  KEMELING, Nathanael R.C. ,  GOUNDAR, Kamal Kishore ,  KUMAR, Davendra ,  STOKHOF, Maarten

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/02063 ,  C23C14/02 ,  C23C16/02 ,  C23C16/36 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed (100) in insulating layers. The layers are then adequately treated with a particular plasma process (101). Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction (115) can occur without significantly filling the pores forming improved interconnects.