公开(公告)号：US20180314160A1

公开(公告)日：2018-11-01

申请号：US15771585

申请日：2016-10-07

Applicant: ASML NETHERLANDS B.V.

Inventor： Martinus Gerardus Maria Johannes MAASSEN ,  Reinder Teun PLUG ,  Kaustuve BHATTACHARYYA

IPC: G03F7/20 ,  G06F17/50

CPC classification number: G03F7/705 ,  G03F7/70625 ,  G03F7/70991

Abstract: Increasingly, metrology systems are integrated within the lithographic apparatuses, to provide integrated metrology within the lithographic process. However, this integration can result in a throughput or productivity impact of the whole lithographic apparatus which can be difficult to predict. It is therefore proposed to provide a simulation model which is operable to acquire throughput information associated with a throughput of a plurality of substrates within a lithographic apparatus, said throughput information comprising a throughput parameter, predict, using a throughput simulator the throughput using the throughput parameter as an input parameter. The throughput simulator may be calibrated using the acquired throughput information. The impact of at least one change of a throughput parameter on the throughput of the lithographic apparatus may be predicted using the throughput simulator.

公开(公告)号：US20210041788A1

公开(公告)日：2021-02-11

申请号：US16965130

申请日：2019-02-19

Applicant: ASML NETHERLANDS B.V.

Inventor： Anton Bernhard VAN OOSTEN ,  Vidya VAENKATESAN ,  James Norman WILEY ,  Reinder Teun PLUG

IPC: G03F7/20

Abstract: A method for inspection of a patterning device. The method includes obtaining (i) patterning device apparatus data of a patterning device making process, (ii) a patterning device substrate map based on the patterning device apparatus data, and (iii) predicted process window limiting pattern locations corresponding to the patterning device based on the patterning device substrate map, and based on the process window limiting pattern locations, guiding a patterning device inspection apparatus to the process window limiting pattern locations for defect inspection.

公开(公告)号：US20190235394A1

公开(公告)日：2019-08-01

申请号：US16257656

申请日：2019-01-25

Applicant: ASML NETHERLANDS B.V.

Inventor： Reinder Teun PLUG ,  Maurits VAN DER SCHAAR

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70625 ,  G03F7/7015 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  G03F9/7088 ,  H01L23/544

Abstract: A method of patterning of at least a layer in a semiconductor device, the method including a patterning step by a patterning means, wherein the patterned layer comprises sensing radiation transmissive portions and sensing radiation blocking portions.