公开(公告)号：US20160018742A1

公开(公告)日：2016-01-21

申请号：US14867606

申请日：2015-09-28

Applicant: ASML Netherlands B.V.

Inventor： Marcus Adrianus VAN DE KERKHOF ,  Leonardus Henricus Marie VERSTAPPEN

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/705

Abstract: The overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.

Abstract translation: 测量scribelane中目标的重叠误差。 由于例如对曝光处理的不同响应，芯片区域中所需特征的覆盖误差可能与此不同。 使用模型来模拟这些差异，从而更准确地测量所确定的特征的覆盖误差。

公开(公告)号：US20170160073A1

公开(公告)日：2017-06-08

申请号：US15432684

申请日：2017-02-14

Applicant: ASML Netherlands B.V.

Inventor： Wouter Lodewijk ELINGS ,  Franciscus Bernardus Maria VAN BILSEN ,  Christianus Gerardus Maria DE MOL ,  Everhardus Cornelis MOS ,  Hoite Pieter Theodoor TOLSMA ,  Peter TEN BERGE ,  Paul Jacques VAN WIJNEN ,  Leonardus Henricus Marie VERSTAPPEN ,  Gerald DICKER ,  Reiner Maria JUNGBLUT ,  Li CHUNG-HSUN

IPC: G01B11/00 ,  G03F7/20 ,  G01B11/26

CPC classification number: G01B11/002 ,  G01B11/02 ,  G01B11/14 ,  G01B11/26 ,  G01N21/9501 ,  G01N21/956 ,  G01N21/95607 ,  G03F7/70508 ,  G03F7/70625 ,  G03F7/70633 ,  G05B19/41875 ,  G05B2219/37224 ,  H01L22/20 ,  Y02P90/20 ,  Y02P90/22

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.

公开(公告)号：US20160377992A1

公开(公告)日：2016-12-29

申请号：US15264152

申请日：2016-09-13

Applicant: ASML Netherlands B.V.

Inventor： Marcus Adrianus VAN DE KERKHOF ,  Leonardus Henricus Marie VERSTAPPEN

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/705

Abstract: A lithographic apparatus including an inspection apparatus can measure the overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.

Abstract translation: 可以测量包括检查装置的光刻设备可以测量在scribelane中的目标物的重叠误差。 由于例如对曝光处理的不同响应，芯片区域中所需特征的覆盖误差可能与此不同。 使用模型来模拟这些差异，从而更准确地测量所确定的特征的覆盖误差。