公开(公告)号：CA2113600A1

公开(公告)日：1995-03-31

申请号：CA2113600

申请日：1994-01-17

Applicant: ATI TECHNOLOGIES INC

Inventor： LUM SANFORD S ,  CHEN KEPING ,  WONG SAMUEL L C ,  BENNETT DWAYNE R ,  ALFORD MICHAEL A

IPC: G09G5/36 ,  G09G5/39 ,  G06F15/66

Abstract: The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

公开(公告)号：CA2102942A1

公开(公告)日：1995-03-11

申请号：CA2102942

申请日：1993-11-12

Applicant: ATI TECHNOLOGIES INC

Inventor： LUM SANFORD S ,  CHEN KEPING

IPC: G09G5/02 ,  H04N9/67 ,  G06F15/66

Abstract: The present invention relates to a method of converting signal components of one of a first input three component color model signal and a second input three component color model signal to either one of the first or second three component color model comprised of matrix multiplying input signal components with an array of predetermined transformation parameters to form a multiplied set, vector adding the multiplied set with a predetermined group of offset vectors, whereby signal components of the output signal are produced.

公开(公告)号：CA2108852A1

公开(公告)日：1995-03-11

申请号：CA2108852

申请日：1993-10-20

Applicant: ATI TECHNOLOGIES INC

Inventor： CHEN KEPING ,  LUM SANFORD S ,  WONG SAMUEL L C

IPC: H04N5/262

Abstract: A mixing unit for a video display processor comprised of apparatus for receiving data bits defining a pixel from a destination, apparatus for receiving data bits defining a pixel from a source, apparatus for providing a keying signal, apparatus for providing the destination and source data bits to an output multiplexer, and for providing an output signal from the multiplexer to the destination, and apparatus for selectively inhibiting data writes to the destination in accordance with the keying signal.