General Pattern Blit Source Type
    1.
    发明专利

    公开(公告)号:CA2155177A1

    公开(公告)日:1996-11-09

    申请号:CA2155177

    申请日:1995-08-01

    Abstract: A method of performing a bit block transfer (Bitblt) comprised of reading a pixel data sequence from a source trajectory, writing an X coordinate portion of the pixel data sequence to a destination trajectory, repeating the writing step to the end of a scan line in the event the X coordinate portion is smaller than the scan line, reset the X coordinate following the end of the scan line, reset a Y coordinate and write a successive X coordinate portion of the pixel data sequence to the destination register from an X coordinate start position when the Y coordinate actually advances in the pixel data sequence.

    METHOD OF OPERATING A DRAW ENGINE

    公开(公告)号:CA2134847A1

    公开(公告)日:1996-02-11

    申请号:CA2134847

    申请日:1994-11-01

    Abstract: A method of operating a graphics accelerator draw engine containing registers comprised of saving a state of the registers (contexts) of the draw engine in a predetermined memory area of a memory, loading the draw engine from the memory with the context using a single processor write command, and executing an operation of the draw engine.

    Dual Paged Apertures
    4.
    发明专利

    公开(公告)号:CA2140961A1

    公开(公告)日:1996-03-24

    申请号:CA2140961

    申请日:1995-01-24

    Abstract: A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.

    PLACEMENT OF MEMORY MAPPED REGISTERS AT CONSECUTIVE ADDRESSES

    公开(公告)号:CA2140958A1

    公开(公告)日:1996-03-27

    申请号:CA2140958

    申请日:1995-01-24

    Abstract: A method of moving data into a peripheral system of a computer from a CPU comprised of connecting a port of a memory mapped register of the system to a memory bus of the computer, connecting a port of a CPU to an I/O bus to which at least one peripheral is connected, and connecting a memory access port of the CPU to the memory bus, memory mapping a register of the CPU to multiple consecutive addresses, and applying a repetitive memory data move command to the processor to transfer data into the register of the system through the port of the register of the system via the memory bus from the register of the CPU.

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