公开(公告)号：HK1122425A1

公开(公告)日：2009-05-15

申请号：HK08113741

申请日：2008-12-18

Applicant: ATI TECHNOLOGIES INC ,  ATI

Inventor： LEE EDWARD ,  BOMDICA ARVIND ,  CHEN LIN ,  GAUTHIER CLAUDE ,  HUYNH SAM ,  NG HIOK-TIAQ ,  LING JOHN ,  HO JENNIFER ,  M K SIJI K ,  YEE GIN ,  MACRI JOSEPH

IPC: H04L20060101

Abstract: A method for receiving data comprising responsive to receiving a forward strobe, a forward strobe clock recovery circuit aligning a forward strobe sampling clock; and aligning a data bit sampling clock to track the forward strobe sampling clock during operation.

公开(公告)号：DE602005010810D1

公开(公告)日：2008-12-18

申请号：DE602005010810

申请日：2005-11-02

Applicant: ATI TECHNOLOGIES INC

Inventor： AHMAD SAGHEER ,  SCOTT ERIC ,  MACRI JOSEPH ,  SHIMIZU DAN

IPC: G11C29/36 ,  G11C29/10

公开(公告)号：DE60321612D1

公开(公告)日：2008-07-31

申请号：DE60321612

申请日：2003-02-10

Applicant: ATI TECHNOLOGIES INC ,  ELPIDA MEMORY INC

Inventor： MACRI JOSEPH ,  DRAPKIN OLEG ,  TEMKINE GRIGORI ,  NAGASHIMA OSAMU

IPC: G11C7/10 ,  G11C11/4096

公开(公告)号：WO2007117526A3

公开(公告)日：2008-04-17

申请号：PCT/US2007008438

申请日：2007-04-03

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  MACRI JOSEPH ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  MOREIN STEPHEN ,  CHEN LIN

Inventor： MACRI JOSEPH ,  GAUTHIER CLAUDE ,  LEE MING-JU E ,  MOREIN STEPHEN ,  CHEN LIN

IPC: G06F1/26 ,  G06F1/04

CPC classification number: G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

Abstract translation: 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：WO2007136785A3

公开(公告)日：2008-05-02

申请号：PCT/US2007011964

申请日：2007-05-17

Applicant: ATI TECHNOLOGIES INC ,  MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

Inventor： MACRI JOSEPH ,  MOREIN STEPHEN ,  LEE MING-JU E ,  CHEN LIN

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

Abstract translation: 描述了针对在模拟定时电路初始化和变得可用的时间段期间继续以低功率模式工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。