公开(公告)号：US20140035634A1

公开(公告)日：2014-02-06

申请号：US13567611

申请日：2012-08-06

Applicant: Aatmesh Shrivastava ,  Rajesh Yadav

Inventor： Aatmesh Shrivastava ,  Rajesh Yadav

IPC: H03L7/00

CPC classification number: G01R21/00 ,  H03K17/223 ,  H03L7/00

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract translation: 公开了包括被配置为产生上电复位（POR）脉冲的电路的集成电路（IC）。 IC包括电源检测电路，其被配置为响应于电源信号从第一电平到第二电平的转变而产生感测信号，以及脉冲发生电路与电源检测电路耦合。 脉冲发生电路被配置为基于感测信号产生阈值持续时间的上电复位（POR）脉冲。 IC还包括与脉冲发生电路耦合以接收POR脉冲的复位产生电路。 复位产生电路被配置为基于POR信号和至少一个控制信号产生复位脉冲，其中复位脉冲被配置为用于执行集成电路的一个或多个元件的复位。

公开(公告)号：US20110037527A1

公开(公告)日：2011-02-17

申请号：US12540367

申请日：2009-08-13

Applicant: Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

Inventor： Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

IPC: H03B5/30

CPC classification number: H03B5/06 ,  H03B2200/0094

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract translation: 具有降低启动时间的示例性快速启动晶体振荡器。 示例性振荡器通过增加电路的负电阻来减小启动时间（即，在电源接通之后获得持续的稳定振荡所花费的时间）。 增加负电阻会增加振荡的增长率，从而减少启动时间。 示例性晶体振荡器包括具有负电阻的增益级。 具有并联电容的晶体放置在增益级的反馈环路中。 缓冲器耦合到增益级，使得其阻止晶体分流电容加载增益级，有效地增加增益级的负电阻。 此外，振荡检测和控制电路耦合在晶体和增益级之间。 振荡检测和控制电路在启动期间连接缓冲器，一旦振荡信号达到持续的稳定振荡，就断开缓冲器。

公开(公告)号：US08797072B2

公开(公告)日：2014-08-05

申请号：US14168307

申请日：2014-01-30

Applicant: Aatmesh Shrivastava ,  Rajesh Yadav

Inventor： Aatmesh Shrivastava ,  Rajesh Yadav

IPC: H03L7/06 ,  H03L7/00 ,  H03K17/22 ,  G01R21/00

CPC classification number: G01R21/00 ,  H03K17/223 ,  H03L7/00

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract translation: 公开了包括被配置为产生上电复位（POR）脉冲的电路的集成电路（IC）。 IC包括电源检测电路，其被配置为响应于电源信号从第一电平到第二电平的转变而产生感测信号，以及脉冲发生电路与电源检测电路耦合。 脉冲发生电路被配置为基于感测信号产生阈值持续时间的上电复位（POR）脉冲。 IC还包括与脉冲发生电路耦合以接收POR脉冲的复位产生电路。 复位产生电路被配置为基于POR信号和至少一个控制信号产生复位脉冲，其中复位脉冲被配置为用于执行集成电路的一个或多个元件的复位。

公开(公告)号：US08680901B2

公开(公告)日：2014-03-25

申请号：US13567611

申请日：2012-08-06

Applicant: Aatmesh Shrivastava ,  Rajesh Yadav

Inventor： Aatmesh Shrivastava ,  Rajesh Yadav

IPC: H03L7/06

CPC classification number: G01R21/00 ,  H03K17/223 ,  H03L7/00

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract translation: 公开了包括被配置为产生上电复位（POR）脉冲的电路的集成电路（IC）。 IC包括电源检测电路，其被配置为响应于电源信号从第一电平到第二电平的转变而产生感测信号，以及脉冲发生电路与电源检测电路耦合。 脉冲发生电路被配置为基于感测信号产生阈值持续时间的上电复位（POR）脉冲。 IC还包括与脉冲发生电路耦合以接收POR脉冲的复位产生电路。 复位产生电路被配置为基于POR信号和至少一个控制信号产生复位脉冲，其中复位脉冲被配置为用于执行集成电路的一个或多个元件的复位。

公开(公告)号：US08120439B2

公开(公告)日：2012-02-21

申请号：US12540367

申请日：2009-08-13

Applicant: Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

Inventor： Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

IPC: H03B5/32 ,  H03L5/00

CPC classification number: H03B5/06 ,  H03B2200/0094

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract translation: 具有降低启动时间的示例性快速启动晶体振荡器。 示例性振荡器通过增加电路的负电阻来减小启动时间（即，在电源接通之后获得持续的稳定振荡所花费的时间）。 增加负电阻会增加振荡的增长率，从而减少启动时间。 示例性晶体振荡器包括具有负电阻的增益级。 具有并联电容的晶体放置在增益级的反馈环路中。 缓冲器耦合到增益级，使得其阻止晶体分流电容加载增益级，有效地增加增益级的负电阻。 此外，振荡检测和控制电路耦合在晶体和增益级之间。 振荡检测和控制电路在启动期间连接缓冲器，一旦振荡信号达到持续的稳定振荡，就断开缓冲器。

公开(公告)号：US20110316505A1

公开(公告)日：2011-12-29

申请号：US12821168

申请日：2010-06-23

Applicant: Aatmesh Shrivastava

Inventor： Aatmesh Shrivastava

IPC: G05F1/10

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected at a junction node. Each of the cascoded pairs receives a corresponding level-shifted signal representing the input signal, and generates corresponding driver signals on driver nodes which are coupled to the output node. The driver circuit includes a capacitor connected between one of the driver nodes and the junction node. The capacitor enables the corresponding driver signal to be generated to reach a desired voltage quickly. The output impedance of the output buffer with which the output signal is launched is reduced and more closely matched the impedance of the path on which the output signal is provided. Signal quality of the output signal is thereby improved.

Abstract translation: 输出缓冲器接收输入信号并在输出节点产生输出信号。 输出缓冲器包含驱动电路。 驱动器电路包括连接在连接节点处的两对级联晶体管。 每个级联对接收表示输入信号的对应的电平移位信号，并且在耦合到输出节点的驱动器节点上产生相应的驱动器信号。 驱动器电路包括连接在其中一个驱动器节点和连接节点之间的电容器。 该电容使得可以产生相应的驱动器信号以快速达到所需电压。 输出信号被输出的输出缓冲器的输出阻抗减小并且与提供输出信号的路径的阻抗更紧密地匹配。 从而提高输出信号的信号质量。

公开(公告)号：US09350294B2

公开(公告)日：2016-05-24

申请号：US14594814

申请日：2015-01-12

Applicant: Benton Calhoun ,  Aatmesh Shrivastava

Inventor： Benton Calhoun ,  Aatmesh Shrivastava

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B5/04 ,  H03B5/32 ,  H03B2200/0012 ,  H03B2200/0046 ,  H03B2200/0064 ,  H03B2200/0082 ,  H03L5/00

Abstract: A low voltage crystal oscillator (XTAL) driver with feedback controlled duty cycling for ultra low power biases an amplifier for an XTAL in the sub-threshold operating regime. A feedback control scheme can be used to bias the amplifier for an XTAL biased in the sub-threshold operating regime. The amplifier of a XTAL oscillator can be duty cycled to save power, e.g., the XTAL driver can be turned off to save power when the amplitude of the XTAL oscillation reaches a maximum value in range; but be turned back on when the amplitude of the XTAL oscillation starts to decay, to maintain the oscillation before it stops. In addition or alternatively, a feedback control scheme to duty cycle the amplifier of a XTAL oscillator can be used to monitor the amplitude of the oscillation.

Abstract translation: 具有反馈控制占空比的低电压晶体振荡器（XTAL）驱动器，用于超低功耗偏置用于子阈值操作状态下XTAL的放大器。 可以使用反馈控制方案来偏置放大器以在子阈值操作状态下偏置的XTAL。 XTAL振荡器的放大器可以重复循环以节省功率，例如，当XTAL振荡的幅度达到最大值时，XTAL驱动器可以关闭以节省功耗; 但是当XTAL振荡的振幅开始衰减时，重新开启，以便在停止之前保持振荡。 另外或替代地，可以使用用于对XTAL振荡器的放大器进行占空比的反馈控制方案来监视振荡的幅度。

公开(公告)号：US20140285014A1

公开(公告)日：2014-09-25

申请号：US14213215

申请日：2014-03-14

Applicant: Benton H. Calhoun ,  Aatmesh Shrivastava

Inventor： Benton H. Calhoun ,  Aatmesh Shrivastava

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M2001/009 ,  Y10T307/406

Abstract: In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.

Abstract translation: 在一些实施例中，一种装置包括单电感多输出（SIMO）直流（DC-DC）转换器电路，其中SIMO DC-DC转换器电路具有一组输出节点。 该装置还包括可操作地耦合到SIMO DC-DC转换器电路的全景动态电压缩放（PDVS）电路，其中PDVS电路具有一组操作块，每个操作块与来自一个电源电压的功率块组合 轨从一组供电电压轨。 此外，来自该组输出节点的每个输出节点与来自该组电源电压轨的电源电压轨迹唯一地相关联。

公开(公告)号：US09698685B2

公开(公告)日：2017-07-04

申请号：US14213215

申请日：2014-03-14

Applicant: Benton H Calhoun ,  Aatmesh Shrivastava

Inventor： Benton H Calhoun ,  Aatmesh Shrivastava

IPC: H02M3/158 ,  H02J1/00 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M2001/009 ,  Y10T307/406

Abstract: In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.

公开(公告)号：US20150214955A1

公开(公告)日：2015-07-30

申请号：US14426571

申请日：2013-09-06

Applicant: Benton H. CALHOUN ,  Aatmesh SHRIVASTAVA

Inventor： Benton H. Calhoun ,  Aatmesh Shrivastava

IPC: H03L1/02 ,  H03B5/32

CPC classification number: H03L1/026 ,  G06F1/04 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H03B5/32 ,  H03K3/011 ,  H03K3/0315 ,  H03L1/02 ,  H03L1/021 ,  H03L1/022

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

Abstract translation: 超低功率时钟源包括补偿振荡器和由比较器电路耦合的未补偿振荡器。 在一个示例中，相对于温度，电压，年龄或其他环境参数中的一个或多个的变化，补偿振荡器比未补偿的振荡器更稳定。 无补偿振荡器包括配置为调整未补偿振荡器的工作特性的配置输入。 在一个示例中，使用来自比较器电路的信息来调整来自补偿振荡器和未补偿振荡器的输出信号的比较的未补偿振荡器。