公开(公告)号：US20240112749A1

公开(公告)日：2024-04-04

申请号：US17957498

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick James Shyvers

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/0772 ,  G06F11/0793

Abstract: The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least one processor is also configured to perform a remediation action in response to detecting the mismatch. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240202116A1

公开(公告)日：2024-06-20

申请号：US18068930

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Paul James Moyer ,  Nicholas Dean Lance ,  Sriram Srinivasan ,  Patrick James Shyvers ,  William Louie Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/1044

Abstract: An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

公开(公告)号：US12009047B2

公开(公告)日：2024-06-11

申请号：US17957498

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick James Shyvers

IPC: G11C29/52 ,  G06F11/07 ,  G06F11/10 ,  G11C29/10

CPC classification number: G11C29/52 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1064 ,  G11C29/10

Abstract: The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least one processor is also configured to perform a remediation action in response to detecting the mismatch. Various other methods, systems, and computer-readable media are also disclosed.